Datasheet

Revision history M24C64-W M24C64-R M24C64-F 
40/42 DocID16891 Rev 28
11 Revision history
Table 25. Document revision history
Date Revision Changes
14-Mar-2011 22
Updated information concerning E2, E1, E0 for the WLCSP package:
– note under Figure 3: 5-bump WLCSP connections (top view)
– comment under Figure 5: Device select code
– note 3 under Table 2: Device select code
07-Apr-2011 23
Updated MLP8 package data and Section Figure 56.: WLCSP 5 bumps
package outline.
Added footnote (a) in Section 4.5: Memory addressing.
18-May-2011 24
Updated:
– Figure 3: 5-bump WLCSP connections (top view)
– Table 5: Absolute maximum ratings
– Small text changes
Added:
– Figure 12: Memory cell characteristics
08-Sep-2011 25
Updated:
– Table 21: UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra
thin Fine pitch Dual Flat Package, No lead)
– Figure 14: Maximum R
bus
value versus bus parasitic capacitance
C
bus
) for an I
2
C bus at maximum frequency f
C
= 1MHz
– Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value
versus bus parasitic capacitance (Cbus).
Added t
WLDL
and t
DHWH
in:
– Table 16: 400 kHz AC characteristics
– Table 17: 1 MHz AC characteristics
– Figure :
Minor text changes.
16-Dec-2011 26
Updated A dimension in Table 22: WLCSP 5-bump wafer-length chip-
scale package mechanical data (M24C64-FCS6TP/K).