Datasheet
Table Of Contents
- 1 Description
- 2 Signal description
- 3 Memory organization
- 4 Device operation
- 5 Instructions
- 6 Initial delivery state
- 7 Maximum rating
- 8 DC and AC parameters
- Table 5. Operating conditions (voltage range W)
- Table 6. Operating conditions (voltage range R)
- Table 7. Operating conditions (voltage range F, for devices identified by process letter T)
- Table 8. Operating conditions (voltage range F, for all other devices)
- Table 9. AC measurement conditions
- Figure 11. AC measurement I/O waveform
- Table 10. Input parameters
- Table 11. Cycling performance
- Table 12. Memory cell data retention
- Table 13. DC characteristics (M24C08-W, device grade 6)
- Table 14. DC characteristics (M24C08-R, device grade 6)
- Table 15. DC characteristics (M24C08-F device)
- Table 16. 400 kHz AC characteristics
- Table 17. 100 kHz AC characteristics (I2C Standard mode)
- Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz
- Figure 13. AC waveforms
- 9 Package mechanical data
- Figure 14. TSSOP8 – 8-lead thin shrink small outline, package outline
- Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
- Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
- Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data
- Figure 16. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline
- Table 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data
- Figure 17. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- Table 21. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- Figure 18. M24C08-FCS5TP/S WLCSP package outline
- Table 22. M24C08-FCS5TP/S WLCSP package data
- Figure 19. Thin M24C08-FCT5TP/S WLCSP package outline
- Table 23. Thin M24C08-FCT5TP/S WLCSP package data
- 10 Part numbering
- 11 Revision history

Instructions M24C08-W M24C08-R M24C08-F
16/40 DocID023924 Rev 3
5.1.2 Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A9/A4, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (
WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in
Figure 8. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 8. Write mode sequences with WC = 1 (data write inhibited)
3TOP
3TART
"YTE7RITE $EVSELECT "YTEADDRESS $ATAIN
7#
3TART
0AGE7RITE $EVSELECT "YTEADDRESS $ATAIN $ATAIN
7#
$ATAIN
!)D
0AGE7RITE
CONTgD
7#CONTgD
3TOP
$ATAIN.
!#+ !#+ ./!#+
27
!#+ !#+ ./!#+ ./!#+
27
./!#+ ./!#+