Datasheet
Table Of Contents
- 1 Description
- 2 Signal description
- 3 Memory organization
- 4 Device operation
- 5 Instructions
- 6 Initial delivery state
- 7 Maximum rating
- 8 DC and AC parameters
- Table 5. Operating conditions (voltage range W)
- Table 6. Operating conditions (voltage range R)
- Table 7. Operating conditions (voltage range F, for devices identified by process letter T)
- Table 8. Operating conditions (voltage range F, for all other devices)
- Table 9. AC measurement conditions
- Figure 11. AC measurement I/O waveform
- Table 10. Input parameters
- Table 11. Cycling performance
- Table 12. Memory cell data retention
- Table 13. DC characteristics (M24C08-W, device grade 6)
- Table 14. DC characteristics (M24C08-R, device grade 6)
- Table 15. DC characteristics (M24C08-F device)
- Table 16. 400 kHz AC characteristics
- Table 17. 100 kHz AC characteristics (I2C Standard mode)
- Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz
- Figure 13. AC waveforms
- 9 Package mechanical data
- Figure 14. TSSOP8 – 8-lead thin shrink small outline, package outline
- Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
- Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
- Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data
- Figure 16. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline
- Table 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data
- Figure 17. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- Table 21. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- Figure 18. M24C08-FCS5TP/S WLCSP package outline
- Table 22. M24C08-FCS5TP/S WLCSP package data
- Figure 19. Thin M24C08-FCT5TP/S WLCSP package outline
- Table 23. Thin M24C08-FCT5TP/S WLCSP package data
- 10 Part numbering
- 11 Revision history

Instructions M24C08-W M24C08-R M24C08-F
14/40 DocID023924 Rev 3
5 Instructions
5.1 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in
Figure 7, and waits for the address
byte. The device responds to each address byte with an acknowledge bit, and then waits for
the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle t
W
is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (t
W
), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in
Figure 8.
Table 3. Address byte
A7 A6 A5 A4 A3 A2 A1 A0