Datasheet
Table Of Contents
- 1 Description
- 2 Signal description
- 3 Memory organization
- 4 Device operation
- 5 Instructions
- 6 Initial delivery state
- 7 Maximum rating
- 8 DC and AC parameters
- Table 5. Operating conditions (voltage range W)
- Table 6. Operating conditions (voltage range R)
- Table 7. Operating conditions (voltage range F, for devices identified by process letter T)
- Table 8. Operating conditions (voltage range F, for all other devices)
- Table 9. AC measurement conditions
- Figure 11. AC measurement I/O waveform
- Table 10. Input parameters
- Table 11. Cycling performance
- Table 12. Memory cell data retention
- Table 13. DC characteristics (M24C08-W, device grade 6)
- Table 14. DC characteristics (M24C08-R, device grade 6)
- Table 15. DC characteristics (M24C08-F device)
- Table 16. 400 kHz AC characteristics
- Table 17. 100 kHz AC characteristics (I2C Standard mode)
- Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz
- Figure 13. AC waveforms
- 9 Package mechanical data
- Figure 14. TSSOP8 – 8-lead thin shrink small outline, package outline
- Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
- Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
- Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data
- Figure 16. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline
- Table 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data
- Figure 17. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- Table 21. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- Figure 18. M24C08-FCS5TP/S WLCSP package outline
- Table 22. M24C08-FCS5TP/S WLCSP package data
- Figure 19. Thin M24C08-FCT5TP/S WLCSP package outline
- Table 23. Thin M24C08-FCT5TP/S WLCSP package data
- 10 Part numbering
- 11 Revision history

DocID023924 Rev 3 13/40
M24C08-W M24C08-R M24C08-F Device operation
39
4.5 Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in
Table 2 (on Serial Data (SDA), most significant bit first).
The 8
th
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
th
bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 2. Device select code
Device type identifier
(1)
1. The most significant bit, b7, is sent first.
Chip Enable address RW
b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 0 E2 A9 A8 RW