Datasheet
Table Of Contents
- 1 Description
- 2 Signal description
- 3 Memory organization
- 4 Device operation
- 5 Instructions
- 6 Initial delivery state
- 7 Maximum rating
- 8 DC and AC parameters
- Table 5. Operating conditions (voltage range W)
- Table 6. Operating conditions (voltage range R)
- Table 7. Operating conditions (voltage range F, for devices identified by process letter T)
- Table 8. Operating conditions (voltage range F, for all other devices)
- Table 9. AC measurement conditions
- Figure 9. AC measurement I/O waveform
- Table 10. Input parameters
- Table 11. Cycling performance
- Table 12. Memory cell data retention
- Table 13. DC characteristics (M24C04-W, device grade 6)
- Table 14. DC characteristics (M24C04-R, device grade 6)
- Table 15. DC characteristics (M24C04-F device, grade 6 and grade 5)
- Table 16. 400 kHz AC characteristics
- Table 17. 100 kHz AC characteristics (I2C Standard mode)
- Figure 10. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz
- Figure 11. AC waveforms
- 9 Package mechanical data
- Figure 12. TSSOP8 – 8-lead thin shrink small outline, package outline
- Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
- Figure 13. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
- Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data
- Figure 14. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline
- Table 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data
- Figure 15. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- Table 21. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- 10 Part numbering
- 11 Revision history

DocID023994 Rev 3 31/34
M24C04-W M24C04-R M24C04-F Package mechanical data
33
Figure 15. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead)
1. Drawing is not to scale.
2. The central pad (area E2 by D2 in the above illustration) is internally pulled to V
SS
. It must not be
connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 21. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead)
Symbol
millimeters inches
(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 0.550 0.450 0.600 0.0217 0.0177 0.0236
A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MC) – 1.200 1.600 – 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MC) – 1.200 1.600 – 0.0472 0.0630
e 0.500 – – 0.0197 – –
K (rev MC) – 0.300 – – 0.0118 –
L – 0.300 0.500 – 0.0118 0.0197
L1 – – 0.150 – – 0.0059
L3 – 0.300 – – 0.0118 –
eee
(2)
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
– 0.080 – – 0.0031 –
D
E
ZW_MEeV2
A
A1
eee
L1
e b
D2
L
E2
L3
Pin 1
K
MC