Datasheet

DC and AC parameters M24C04-W M24C04-R M24C04-F
26/34 DocID023994 Rev 3
Table 17. 100 kHz AC characteristics (I
2
C Standard mode)
(1)
1. Values recommended by the I
2
C bus Standard-mode specification for a robust design of the I
2
C bus
application. Note that the M24xxx devices decode correctly faster timings as specified in Table 16: 400 kHz
AC characteristics.
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCL
Clock frequency - 100 kHz
t
CHCL
t
HIGH
Clock pulse width high 4 - µs
t
CLCH
t
LOW
Clock pulse width low 4.7 - µs
t
XH1XH2
t
R
Input signal rise time - 1 µs
t
XL1XL2
t
F
Input signal fall time - 300 ns
t
QL1QL2
(2)
2. Characterized only.
t
F
SDA fall time - 300 ns
t
DXCX
t
SU:DAT
Data in setup time 250 - ns
t
CLDX
t
HD:DAT
Data in hold time 0 - ns
t
CLQX
(3)
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
t
DH
Data out hold time 200 - ns
t
CLQV
(4)
4. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 V
CC
or
0.7 V
CC
, assuming that Rbus × Cbus time constant is within the values specified in Figure 11.
t
AA
Clock low to next data valid (access time) - 3450 ns
t
CHDL
(5)
5. For a reStart condition, or following a Write cycle.
t
SU:STA
Start condition setup time 4.7 - µs
t
DLCL
t
HD:STA
Start condition hold time 4 - µs
t
CHDH
t
SU:STO
Stop condition setup time 4 - µs
t
DHDL
t
BUF
Time between Stop condition and next Start
condition
4.7 - µs
t
W
t
WR
Write time - 5 ms
t
NS
(2)
Pulse width ignored (input filter on SCL and
SDA), single glitch
- 100 ns