Datasheet
Table Of Contents
- 1 Description
- 2 Signal description
- 3 Memory organization
- 4 Device operation
- 5 Instructions
- 6 Initial delivery state
- 7 Maximum rating
- 8 DC and AC parameters
- Table 5. Operating conditions (voltage range W)
- Table 6. Operating conditions (voltage range R)
- Table 7. Operating conditions (voltage range F, for devices identified by process letter T)
- Table 8. Operating conditions (voltage range F, for all other devices)
- Table 9. AC measurement conditions
- Figure 9. AC measurement I/O waveform
- Table 10. Input parameters
- Table 11. Cycling performance
- Table 12. Memory cell data retention
- Table 13. DC characteristics (M24C04-W, device grade 6)
- Table 14. DC characteristics (M24C04-R, device grade 6)
- Table 15. DC characteristics (M24C04-F device, grade 6 and grade 5)
- Table 16. 400 kHz AC characteristics
- Table 17. 100 kHz AC characteristics (I2C Standard mode)
- Figure 10. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz
- Figure 11. AC waveforms
- 9 Package mechanical data
- Figure 12. TSSOP8 – 8-lead thin shrink small outline, package outline
- Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
- Figure 13. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
- Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data
- Figure 14. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline
- Table 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data
- Figure 15. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- Table 21. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- 10 Part numbering
- 11 Revision history

DocID023994 Rev 3 25/34
M24C04-W M24C04-R M24C04-F DC and AC parameters
33
Table 16. 400 kHz AC characteristics
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCL
Clock frequency - 400 kHz
t
CHCL
t
HIGH
Clock pulse width high 600 - ns
t
CLCH
t
LOW
Clock pulse width low 1300 - ns
t
QL1QL2
(1)
1. Characterized only, not tested in production.
t
F
SDA (out) fall time 20
(2)
2. With C
L
= 10 pF.
300 ns
t
XH1XH2
t
R
Input signal rise time
(3)
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C
< 400 kHz.
(3)
ns
t
XL1XL2
t
F
Input signal fall time
(3) (3)
ns
t
DXCX
t
SU:DAT
Data in set up time 100 - ns
t
CLDX
t
HD:DAT
Data in hold time 0 - ns
t
CLQX
(4)
4. The min value for t
CLQX
(Data out hold time) of the M24xxx devices offers a safe timing to bridge the
undefined region of the falling edge SCL.
t
DH
Data out hold time 100 - ns
t
CLQV
(5)
5. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 V
CC
or
0.7 V
CC
, assuming that R
bus
× C
bus
time constant is within the values specified in Figure 10.
t
AA
Clock low to next data valid (access time) - 900 ns
t
CHDL
t
SU:STA
Start condition setup time 600 - ns
t
DLCL
t
HD:STA
Start condition hold time 600 - ns
t
CHDH
t
SU:STO
Stop condition set up time 600 - ns
t
DHDL
t
BUF
Time between Stop condition and next Start
condition
1300 - ns
t
W
t
WR
Write time - 5 ms
t
NS
(1)
Pulse width ignored (input filter on SCL and
SDA) - single glitch
- 100 ns