Datasheet

M24C16, M24C08, M24C04, M24C02, M24C01
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SUMMARY DESCRIPTION
These I²C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 2048/1024/512/256/128 x 8 (M24C16,
M24C08, M24C04, M24C02 and M24C01).
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
Figure 2. Logic Diagram
I²C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I²C bus definition.
The device behaves as a slave in the I²C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write
bit (RW) (as de-
scribed in Table 3.), terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Table 2. Signal Names
Figure 3. 8-Pin Package Connections (Top View)
Note: 1. NC = Not Connected
2. See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1.
AI02033
3
E0-E2 SDA
V
CC
M24Cxx
WC
SCL
V
SS
E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC
Write Control
V
CC
Supply Voltage
V
SS
Ground
SDAV
SS
SCL
WC
V
CC
/ E2
AI02034E
M24Cxx
1
2
3
4
8
7
6
5
/ E2/ E2/ E2NC
/ E1
/ E1/ E1/ NCNC
/ E0
/ E0/ NC/ NCNC
/1Kb
/2Kb/4Kb/8Kb16Kb