Datasheet

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M24C16, M24C08, M24C04, M24C02, M24C01
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be con-
nected from Serial Clock (SCL) to V
CC
. (Figure 5.
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
CC
. (Fig-
ure 5. indicates how the value of the pull-up resis-
tor can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs must be tied to V
CC
or V
SS
, to establish the
Device Select Code as shown in Figure 4.
Figure 4. Device Select Code
Write Control (WC
). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write opera-
tions are disabled to the entire memory array when
Write Control (WC
) is driven High. When uncon-
nected, the signal is internally read as V
IL
, and
Write operations are allowed.
When Write Control (WC
) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Supply voltage (V
CC
)
Operating supply voltage V
CC
. Prior to select-
ing the memory and issuing instructions to it, a val-
id and stable V
CC
voltage must be applied: this
voltage must be a DC voltage within the specified
[V
CC
(min), V
CC
(max)] range, as defined in Table
6. and Table 7. In order to secure a stable DC sup-
ply voltage, it is recommended to decouple the
V
CC
line with a suitable capacitor (usually of the
order of 10nF to 100nF) close to the V
CC
/V
SS
package pins.
The V
CC
voltage must remain stable and valid until
the end of the transmission of the instruction and,
for a Write instruction, until the completion of the
internal write cycle (t
W
).
Internal Device Reset. In order to prevent inad-
vertent Write operations during Power-up, a Pow-
er On Reset (POR) circuit is included. At Power-up
(continuous rise of V
CC
), the device does not re-
spond to any instruction until V
CC
has reached the
Power On Reset threshold voltage (this threshold
is lower than the minimum V
CC
operating voltage
defined in Table 6. and Table 7.).
When V
CC
has passed the POR threshold, the de-
vice is reset and in the Standby Power mode
Power-down. At Power-down (where V
CC
de-
creases continuously), as soon as V
CC
drops from
the operating voltage range below the Power On
Reset threshold voltage, the device stops re-
sponding to any instruction sent to it.
During Power-down, the device must be deselect-
ed and in the Standby Power mode (that is there
should be no internal Write cycle in progress).
Ai11650
V
CC
M24Cxx
V
SS
E
i
V
CC
M24Cxx
V
SS
E
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