Datasheet
Table Of Contents
- 1 Description
- 2 Signal description
- 3 Memory organization
- 4 Device operation
- 5 Instructions
- 6 Initial delivery state
- 7 Maximum rating
- 8 DC and AC parameters
- Table 5. Operating conditions (voltage range W)
- Table 6. Operating conditions (voltage range R)
- Table 7. Operating conditions (voltage range F, for devices identified by process letter T)
- Table 8. Operating conditions (voltage range F, for all other devices)
- Table 9. AC measurement conditions
- Figure 9. AC measurement I/O waveform
- Table 10. Input parameters
- Table 11. Cycling performance
- Table 12. Memory cell data retention
- Table 13. DC characteristics (M24C01/02-W, device grade 6)
- Table 14. DC characteristics (M24C01/02-R, device grade 6)
- Table 15. DC characteristics (M24C02-F, device grade 6)
- Table 16. 400 kHz AC characteristics
- Table 17. 100 kHz AC characteristics (I2C Standard mode)
- Figure 10. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz
- Figure 11. AC waveforms
- 9 Package mechanical data
- Figure 12. TSSOP8 – 8-lead thin shrink small outline, package outline
- Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
- Figure 13. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
- Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package data
- Figure 14. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline
- Table 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data
- Figure 15. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- Table 21. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch Dual Flat Package, No lead)
- 10 Part numbering
- 11 Revision history
Instructions M24C01/02-W M24C01/02-R M24C02-F
14/34 DocID024020 Rev 2
5.1.1 Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (
WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in
Figure 5.
Figure 5. Write mode sequences with WC = 0 (data write enabled)
Stop
Start
Byte Write Dev Select Byte address
Data in
WC
Start
Page Write Dev Select Byte address Data in 1 Data in 2
WC
Data in 3
AI02804c
Page Write
(cont'd)
WC (cont'd)
Stop
Data in N
ACK
R/W
ACK ACK
ACK ACK ACK ACK
R/W
ACKACK