Datasheet

DocID024020 Rev 2 13/34
M24C01/02-W M24C01/02-R M24C02-F Instructions
33
5 Instructions
5.1 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in
Figure 5, and waits for the address
byte. The device responds to each address byte with an acknowledge bit, and then waits for
the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10
th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle t
W
is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (t
W
), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in
Figure 6.
Table 3. Address byte
A7 A6 A5 A4 A3 A2 A1 A0