Datasheet

11/24
M24512
Figure 9. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 4
th
bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC
) signal.
After the successful completion of a Read opera-
tion, the device’s internal address counter is incre-
mented by one, to point to the next byte address.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 9.) but
without sending a Stop condition. Then,
the bus master sends another Start condition, and
repeats the Device Select Code, with the Read/
Write
bit (RW) set to 1. The device acknowledges
this, and outputs the contents of the addressed
byte. The bus master must
not acknowledge the
byte, and terminates the transfer with a Stop con-
dition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the Read/Write
bit (RW) set
to 1. The device acknowledges this, and outputs
the byte addressed by the internal address
counter. The counter is then incremented. The bus
master terminates the transfer with a Stop condi-
tion, as shown in Figure 9.,
without acknowledging
the byte.
START
DEV SEL * BYTE ADDR BYTE ADDR
START
DEV SEL DATA OUT 1
AI01105C
DATA OUT N
STOP
START
CURRENT
ADDRESS
READ
DEV SEL DATA OUT
RANDOM
ADDRESS
READ
STOP
START
DEV SEL * DATA OUT
SEQUENTIAL
CURRENT
READ
STOP
DATA OUT N
START
DEV SEL * BYTE ADDR BYTE ADDR
SEQUENTIAL
RANDOM
READ
START
DEV SEL * DATA OUT 1
STOP
ACK
R/W
NO ACK
ACK
R/W
ACK ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK