Datasheet

DC and AC parameters M24512-W M24512-R M24512-DR M24512-DF
30/40 Doc ID 16459 Rev 26
Table 17. 1 MHz AC characteristics
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCL
Clock frequency 0 1 MHz
t
CHCL
t
HIGH
Clock pulse width high 300 - ns
t
CLCH
t
LOW
Clock pulse width low 400 - ns
t
XH1XH2
t
R
Input signal rise time
(1)
1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be less than 120 ns when f
C
<1MHz.
(1)
ns
t
XL1XL2
t
F
Input signal fall time
(1) (1)
ns
t
QL1QL2
(2)
2. Characterized only, not tested in production.
t
F
SDA (out) fall time - 120 ns
t
DXCX
t
SU:DAT
Data in setup time 80 - ns
t
CLDX
t
HD:DAT
Data in hold time 0 - ns
t
CLQX
(3)
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
t
DH
Data out hold time 50 - ns
t
CLQV
(4)
4. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 V
CC
or
0.7 V
CC
, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13.
t
AA
Clock low to next data valid (access time) - 500 ns
t
CHDL
t
SU:STA
Start condition setup time 250 - ns
t
DLCL
t
HD:STA
Start condition hold time 250 - ns
t
CHDH
t
SU:STO
Stop condition setup time 250 - ns
t
DHDL
t
BUF
Time between Stop condition and next Start
condition
500 - ns
t
WLDL
(5)(2)
5. WC=0 set up time condition to enable the execution of a WRITE command.
t
SU:WC
WC set up time (before the Start condition) 0 - µs
t
DHWH
(6)(2)
6. WC=0 hold time condition to enable the execution of a WRITE command.
t
HD:WC
WC hold time (after the Stop condition) 1 - µs
t
W
t
WR
Write time - 5 ms
t
NS
(2)
Pulse width ignored (input filter on SCL and
SDA)
-80
(7)
7. 50100 ns for devices identified by process letter A.
ns