Datasheet

M24512-W M24512-R M24512-DR M24512-DF DC and AC parameters
Doc ID 16459 Rev 26 29/40
Table 16. 400 kHz AC characteristics
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCL
Clock frequency - 400 kHz
t
CHCL
t
HIGH
Clock pulse width high 600 - ns
t
CLCH
t
LOW
Clock pulse width low 1300 - ns
t
QL1QL2
(1)
1. Characterized only, not tested in production.
t
F
SDA (out) fall time 20
(2)
2. With C
L
= 10 pF.
300 ns
t
XH1XH2
t
R
Input signal rise time
(3)
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C
< 400 kHz.
(3)
ns
t
XL1XL2
t
F
Input signal fall time
(3) (3)
ns
t
DXCH
t
SU:DAT
Data in set up time 100 - ns
t
CLDX
t
HD:DAT
Data in hold time 0 - ns
t
CLQX
(4)
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
t
DH
Data out hold time 100 - ns
t
CLQV
(5)
5. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3V
CC
or
0.7V
CC
, assuming that R
bus
× C
bus
time constant is within the values specified in Figure 12.
t
AA
Clock low to next data valid (access time) - 900 ns
t
CHDL
t
SU:STA
Start condition setup time 600 - ns
t
DLCL
t
HD:STA
Start condition hold time 600 - ns
t
CHDH
t
SU:STO
Stop condition set up time 600 - ns
t
DHDL
t
BUF
Time between Stop condition and next Start
condition
1300 - ns
t
WLDL
(6)(1)
6. WC=0 set up time condition to enable the execution of a WRITE command.
t
SU:WC
WC set up time (before the Start condition) 0 - µs
t
DHWH
(7)(1)
7. WC=0 hold time condition to enable the execution of a WRITE command.
t
HD:WC
WC hold time (after the Stop condition) 1 - µs
t
W
t
WR
Internal Write cycle duration - 5 ms
t
NS
(1)
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-80ns