Datasheet

LNBH25L Pin configuration
Doc ID 022634 Rev 2 9/28
3 Pin configuration
Figure 5. Pin connections (top view)
AM10461v1
GND
GNDNC DSQIN
VUP
VCC
PGND
GND
NC
LX
SDA
ISEL
NCNC
GND
NC
NC
VOUT
NC
VBYP
GND
ADDR NC
SCL
1
2
3
4
5
6
18
17
16
15
14
13
7 8 9 121110
192021222324
LNBH25L
Table 2. Pin description
Pin n° Symbol Name Pin function
3 LX N-MOS drain Integrated N-channel Power MOSFET drain.
4 P-GND Power ground
DC-DC converter power ground. To be connected directly to the
Epad.
6 ADDR Address setting
Two I²C bus addresses available by setting the address pin level
voltage. See
Ta bl e 1 5 .
7 SCL Serial clock Clock from I²C bus.
8 SDA Serial data Bi-directional data from/to the I²C bus.
9 ISEL Current selection
The resistor “RSEL” connected between ISEL and GND defines the
linear regulator current limit threshold. Refer to
Section 2.4 .
2,15, 18, 19,
23
GND Analog ground Analog circuits ground. To be connected directly to the Epad.
16 BYP Bypass capacitor
Needed for internal pre-regulator filtering. The BYP pin is intended
only to connect an external ceramic capacitor. Any connection of
this pin to external current or voltage sources may cause permanent
damage to the device.
17 V
CC
Supply input 8 to 16 V IC DC-DC power supply.
20 V
OUT
LNB output port
Output of the integrated very low drop linear regulator. See
Ta bl e 1 3
for voltage selection and description.
21 V
UP
Step-up voltage
Input of the linear post-regulator. The voltage on this pin is
monitored by the internal step-up controller to keep a minimum
dropout across the linear pass transistor.