Datasheet

LNBH23L software description LNBH23L
18/25 Doc ID 15335 Rev 4
Values are typical unless otherwise specified.
x = don’t care.
7.5 Power-on I²C interface reset
I²C interface built in LNBH23L is automatically reset at power-on. As long as the V
CC
stays
below the under voltage lockout (UVL) threshold (6.7 V), the interface does not respond to
any I²C command and the system register (SR) is initialized to all zeroes, thus keeping the
power blocks disabled. Once the V
CC
rises above 7.3 V typ. The I²C interface becomes
operative and the SR can be configured by the main microprocessor. This is due to 500 mV
of hysteresis provided in the UVL threshold to avoid false retriggering of the power-on reset
circuit.
7.6 Address pin
It is possible to select two I²C interface addresses by means of ADDR pin. This pin is TTL
compatible and can be set as per address pin characteristics Ta ble 1 0.
7.7 DiSEqC™ implementation
LNBH23L helps system designer to implement DiSEqC 1.x protocol by allowing an easy
PWK modulation of the 22 kHz carrier through the EXTM and V
oTX
pins. Full compliance of
the system to the specification is thus not implied by the bare use of the LNBH23L (see
Figure 3, Figure 4 and Figure 5).
Table 7. Register
TEST1 TEST2 TEST3 LLC VSEL EN OTF OLF Function
These bits are read
exactly the same as
they were left after
last write operation
0T
J
< 135°C, normal operation
1T
J
> 150°C, power blocks disabled
0I
O
< I
OMAX
, normal operation
1I
O
> I
OMAX
, Overload protection triggered
XX X
These bits status must be disregarded by the
MCU.