Datasheet

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This is information on a product in full production.

September 2012 Doc ID 14608 Rev 3 1/8

LFTVS18-1F3

Low forward voltage Transil™, transient voltage suppressor

Datasheet  production data

Features

■ Strong ESD and EOS protection

■ Very low clamping factor V

■

Unidirectional device

■ Fast response time

■ Very thin package

■ Very small PCB area

■ RoHS compliant

Complies with the following standards:

■ IEC 61000-4-2 level 4

–

±15 kV (air discharge)

–

±8 kV (contact discharge)

Description

The LFTVS18-1F3 is a single line diode designed

specifically for the protection of integrated circuits

in portable equipment and miniaturized

electronics devices subject to ESD and EOS

transient overvoltages.

Figure 1. Pin configuration (bump side)

Figure 2. Device configuration

TM: Transil is a trademark of STMicroelectronics

Flip Chip

(4 bumps)

A1 and A2

B1 and B2

www.st.com

Summary of content (8 pages)

PAGE 1
LFTVS18-1F3 Low forward voltage Transil™, transient voltage suppressor Datasheet  production data Features ■ Strong ESD and EOS protection ■ Very low clamping factor VCL/VBR ■ Unidirectional device ■ Fast response time ■ Very thin package ■ Very small PCB area ■ RoHS compliant Flip Chip (4 bumps) Figure 1.
PAGE 2
Characteristics 1 LFTVS18-1F3 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Test condition PPP Peak pulse power dissipation (8/20 µs pulse) IFSM Non repetitive surge peak forward tp = 10 ms, Tj initial = Tamb current Tj Value Unit 350 W 5 A 125 °C -55 to +150 °C Tj initial = Tamb Maximum operating junction temperature Tstg Figure 3.
PAGE 3
LFTVS18-1F3 Figure 4. Characteristics Peak pulse power versus initial junction temperature (pulse 8/20 µs) Figure 5. PPP (W) 1000.0 200.0 800.0 160.0 600.0 120.0 400.0 80.0 Peak pulse power versus initial junction temperature (pulse 10/1000 µs) PPP (W) 40.0 200.0 Tj(°C) Tj(°C) 0.0 0.0 0 Figure 6. 25 50 75 100 125 150 Peak pulse power versus exponential pulse duration 0 25 Figure 7. PPP(W) 10000 10.0 100 1.0 tp(µs) 10.
PAGE 4
Characteristics LFTVS18-1F3 Figure 10. Junction capacitance versus line voltage (typical values) Figure 11. Junction capacitance versus frequency for different bias voltages (P = -12 dBm) Capacitance(pF) 200 200 F=1 MHz VOSC=30mVRMS Vr=0 à 12V TJ=25°C 150 Capacitance(pF) 180 160 140 120 100 100 80 60 50 40 0.0V 4.0V 8.0V 12.0V 20 Voltage(V) 1M 1 2 3 4 5 6 7 8 9 10 F (Hz) 0 0 0 2.0V 6.0V 10.0V 14.0V 11 3M 10M 30M 100M 12 Figure 12.
PAGE 5
LFTVS18-1F3 2 Ordering information scheme Ordering information scheme Figure 16.
PAGE 6
Package information 3 LFTVS18-1F3 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 605 µm ± 55 0.77 mm ± 30 µm 400 µm ± 40 185 µm ± 10 400 µm ± 40 Figure 17. Package dimensions 205 µm ± 40 185 µm ± 10 0.77 mm ± 30 µm 255 µm ± 40 Figure 18.
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LFTVS18-1F3 Ordering information Dot identifying Pin A1 location 2.0 ± 0.05 Ø 1.55 ± 0.05 4.0 ± 0.1 3.5 ±- 0.05 0.87 ±0.05 8.0 ± 0.3 0.20 ± 0.05 EM z y ww EM z y ww EM z y ww 0.69 ± 0.05 EM z y ww EM z y ww EM z y ww 0.87 ±0.05 2.0 ± 0.1 User direction of unreeling All dimensions in mm Note: 1.75 ± 0.1 Figure 20.
PAGE 8
LFTVS18-1F3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.