Datasheet
Table Of Contents
- Figure 1. Typical application circuit
- 1 Pin settings
- 2 Maximum ratings
- 3 Electrical characteristics
- 4 Functional description
- 5 Application notes - buck conversion
- 5.1 Closing the loop
- 5.2 GCO(s) control to output transfer function
- 5.3 Error amplifier compensation network
- 5.4 LED small signal model
- 5.5 Total loop gain
- 5.6 Compensation network design
- 5.7 Example of system design
- 5.8 Dimming operation
- 5.9 Component selection
- 5.10 Layout considerations
- 5.11 Thermal considerations
- 5.12 Short-circuit protection
- 5.13 Application circuit
- 6 Application notes - alternative topologies
- 7 Package mechanical data
- 8 Ordering information
- 9 Revision history
Application notes - alternative topologies LED5000
44/51 Doc ID 023951 Rev 1
6.4 Compensation network design for alternative topologies
The small signal analysis for the alternative topologies can be written as:
Equation 74
that shares similar terms with
Equation 1
which is valid for the buck (see
Equation 1
). In
addition K
DX
depends on the topology (different for boost and buck-boost) and ω
Z_RHP
(
Equation 75
) is a zero in the right half plane:
Equation 75
The RHP (right half plane) zero has the same 20 dB/dec rising gain magnitude as a
conventional zero, but with 90 degree phase drop instead of lead. This characteristic cannot
be compensated with the error amplifier network so the loop gain is designed to roll off at
lower frequency in order to keep its contribution outside the small signal analysis.
ω
Z_RHP
(see
Equation 75
) depends on the equivalent output resistance, inductor value and
the duty cycle. As a consequence the minimum
ω
Z_RHP
over the input voltage range
determines the maximum system bandwidth:
Equation 76
the system phase margin depends on K.
This paragraph provides the equations to calculate the components of the compensation
network once selected the power components and given the BW specification.
Table 10: BB and boost parameters
summarizes the K
D
, K
m
, K parameters useful for the
next calculations of the compensation network.
The DC gain of the total small loop is:
Equation 77
where G
m
is the error amplifier transconductance, R
EA
the equivalent output resistance of
the error amplifier, R
CS
the internal current sense gain (for these parameters refer to
Table 5: Electrical characteristics
), R
S
the sensing resistor value, and K
D
can be calculated
from
Tabl e 10
The calculation of the components composing the compensation network depends on the
relative position of the pole f
p
(see
Equation 3
) and the designed bandwidth BW.
G
CO
s()
R
LOAD
R
CS
------------------
1D–()
K
Dx
------------------
1
s
ω
Z_RHP
------------------–
⎝⎠
⎛⎞
1
s
ω
z
-----+
⎝⎠
⎛⎞
⋅
1
s
ω
p
-----+
⎝⎠
⎛⎞
-------------------------------------------------------------
F
H
s()⋅⋅ ⋅=
ω
Z_RHP
R
OUT
1D–()
2
⋅
L
-------------------------------------------=
BW BW
MAX
≤
1
K
----
ω
Z_RHP_MIN
2 π⋅
-----------------------------
⋅
f
SW
6
---------«=
A
0
G
m
R
EA
1D–()
R
S
R
CS
-----------
1
K
D
-------
⋅⋅ ⋅⋅=