Datasheet

SPI control and status register L99MC6
40/32 Doc ID 16523 Rev 2
9.4.3 Example 3: Open-load detection in off-state in bridge configuration
From Table 40 and Table 41 follow that the value F8h is written at RAM address 01h (control
register 1).
Table 42 describe more in detail the data byte structure.
Hereafter the actions linked to each value of bit or group of bits:
● ENCP = 1: Charge pump stays activated
● CH5[2:0] = 111b: Channel 5 is off, open-load detection in off-state enabled
● BRIDGE_2&5 = 1: Bridge mode for channel 2 and channel 5 activated
● CH2[2:0] = 000b: Channel 2 is off, open-load detection in off-state disabled
From Table 43 and Table 44 follow that the value 0Ah is written at RAM address 02h
(control register 2).
Table 45 describe more in detail the data byte structure.
Table 40. Command byte 1 - example 3
MSB LSB
Operating code Address
00000001
Table 41. Data byte 1 - example 3
MSB LSB
1 1 111 0 0 0
Table 42. Data byte description 1 - example 3
ENCP
CH5
[2]
CH5
[1]
CH5
[0]
Bridge
2&5
CH2
[2]
CH2
[1]
CH2
[0]
11111000
Table 43. Command byte 2 - example 3
MSB LSB
Operating code Address
00000010
Table 44. Data byte 2 - example 3
MSB LSB
0 0 001 0 1 0