Datasheet

SPI control and status register L99MC6
38/32 Doc ID 16523 Rev 2
9.4.2 Example 2: Bridge mode configuration
From Table 34 and Table 35 follow that the value A8h is written at RAM address 01h
(control register 1).
Table 36 describe more in detail the data byte structure.
Hereafter the actions linked to each value of bit or group of bits:
● ENCP = 1: Charge pump stays activated
● CH5[2:0] = 010b: Channel 5 is on, PWM disabled, overcurrent recovery mode
disabled, low slew rate
● BRIDGE_2&5 = 1: Bridge mode for channel 2 and channel 5 activated
● CH2[2:0] = 000b: Channel 2 is off, open-load detection in off-state disabled
From Table 37 and Table 38 follow that the value 0Ah is written at RAM address 02h
(control register 2).
Table 39 describe more in detail the data byte structure.
Table 34. Command byte 1 - example 2
MSB LSB
Operating code Address
00000001
Table 35. Data byte 1 - example 2
MSB LSB
1 0 101 0 0 0
Table 36. Data byte description 1 - example 2
ENCP
CH5
[2]
CH5
[1]
CH5
[0]
Bridge
2&5
CH2
[2]
CH2
[1]
CH2
[0]
10101000
Table 37. Command byte 2 - example 2
MSB LSB
Operating code Address
00000010
Table 38. Data byte 2 - example 2
MSB LSB
0 0 001 0 1 0