Datasheet

L99MC6 SPI control and status register
Doc ID 16523 Rev 2 35/32
Table 25. Control register 1
Adress Access
Data Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Channel 2&5 control
01h R/W ENCP
CH5
[2]
CH5
[1]
CH5
[0]
Bridge
2&5
CH2
[2]
CH2
[1]
CH2
[0]
Default 10000000
Table 26. Control register 2
Adress Access
Data Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Channel 1&4 control
02h R/W DISCP
CH4
[2]
CH4
[1]
CH4
[0]
Bridge
1&4
CH1
[2]
CH1
[1]
CH1
[0]
Default 00000000
Table 27. Status register 0
Adress Access
Data Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Open-load, thermal status
04h R TSD TWARN
OL
CH6
OL
CH5
OL
CH4
OL
CH3
OL
CH2
OL
CH1
Table 28. Status register 1
Adress Access
Data Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Overcurrent, thermal status
05h R TSD TWARN
OC
CH6
OC
CH5
OC
CH4
OC
CH3
OC
CH2
OC
CH1