Datasheet

Functional description of the SPI L99MC6
30/32 Doc ID 16523 Rev 2
Operating code definition
The <Write mode> and <Read mode> operations allow access to the RAM of the device,
that is write to control registers or read status information.
A <Read and Clear Status> operation addressed to a device specific status register reads
back and subsequently clear this status register. A <Read and Clear Status> operation with
address 3FH clears all status registers at a time.
A <Read and Clear Status> operation addressed to an unused RAM address or
configuration register address is identical to a <Read mode> operation (in case of unused
RAM address, the second byte is equal to 00H).
<Read Device Information> allows access to the ROM area which contains device related
information such as the product family, product name, silicon version and register width.
8.2.3 Global status register
Table 15. Operating code definition
OC1 OC0 Meaning
0 0 <Write mode>
0 1 <Read mode>
1 0 <Read and Clear Status>
1 1 <Read Device Information>
Table 16. Global status register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Global error flag
(GEF)
Communication
error
Chip reset
TSD
Chip overload
Temperature
warning
Open-load
detected
Overcurrent
detected
Unused
Table 17. Global status register description
Bit Description Polarity Comment
0 Unused Active high Always returns ‘0’
1 Overcurrent detected Active high Set by any overcurrent event
2 Open-load detected Active high Set by any open-load event
3 Temperature warning Active high -
4
Thermal shutdown / chip
overload
Active high -
5 Chip reset Active low
Activated by all internal reset events that change
device state or configuration registers (for
example software reset, V
CC
undervoltage, etc.).
The bit is cleared after a valid communication
with any register. This bit is initially ‘0’ and is set
to ‘1’ by a valid SPI communication