Datasheet

Block diagram and pin description L99H01
8/53 DocID15567 Rev 6
9CLK
Serial clock input: this input controls the internal shift register of the
SPI and requires CMOS logic levels.This input has a pull-down
current.
10 DI
Serial data in: the input requires CMOS logic levels and receives serial
data from the microcontroller. The data is an 8-bit control word and the
most significant bit (MSB, bit 7) is transferred first. This input has a
pull-down current.
11 DO
Serial data out: the diagnosis data is available via the SPI and this
tristate-output. The output remains in tristate, if the chip is not selected
by the input CSN (CSN = high).
12, 14, 19,
20, 22
NC Not connected.
13 CSO Current sense amplifier output: V
CC
compatible.
15 CSI1+ Current sense amplifier input: positive input 1, multiplexible.
16 CSI1- Current sense amplifier input: negative input 1, multiplexible.
17 CSI2+ Current sense amplifier input: positive input 2, multiplexible.
18 CSI2- Current sense amplifier input: negative input 2, multiplexible.
21 TS/ ACT_OFF Thermal sensor interface or input to switch all driver active off.
23 GL2 Gate driver for PowerMOS low-side switch in halfbridge 2.
24 SL2 Source of low-side switch in halfbridge 2.
25 GH2 Gate driver for PowerMOS high-side switch in halfbridge 2.
26 SH2 Source/drain of halfbridge 2.
27 SL1 Source of low-side switch in halfbridge 1.
28 GL1 Gate driver for PowerMOS low-side switch in halfbridge 1.
29 SH1 Source/drain of halfbridge 1.
30 GH1 Gate driver for PowerMOS high-side switch in halfbridge 1.
31 CP Charge pump output.
32 CP2+ Charge pump pin for capacitor 2, positive side.
33 CP2- Charge pump pin for capacitor 2, negative side.
34 CP1+ Charge pump pin for capacitor 1, positive side.
35 CP1- Charge pump pin for capacitor 1, negative side.
36 V
S
Power supply voltage (external reverse protection required).
For EMI reason a ceramic capacitor as close as possible to GND is
recommended.
Table 2. Pin definitions and functions (continued)
Pin Symbol Function