Datasheet

Functional description of the SPI L99H01 34/53 DocID15567 Rev 6
4.3 Device memory map
4.3.1 Control and status (RAM) address map
4.3.2 Device (ROM) address map (access with OC0 and OC1 set to ‘1’)
Table 28. Control and status (RAM) address map
Name Access
Address Content
A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Stat Reg0Read/ Clear000000DS_MON_3DS_MON_2DS_MON_1DS_MON_0 0 0 OT_EXTCP_LOW
Appl Reg1Read/ Write000001 RWD FW_PAS OFF_CALCLK_SPCTR OVT
OV_UV_R
D
DIAG_1 DIAG_0
Appl Reg2Read/ Write000010 RWD COPT_2 COPT_1 COPT_0 FW MCSA GCSA_1GCSA_0
Appl Reg3Read/ Write000011 RWD EXT_TS EXTTH_5 EXTTH_4EXTTH_3EXTTH_2EXTTH_1EXTTH_0
Table 29. Device (ROM) address map (access with OC0 and OC1 set to ‘1’)
Name Access
Address Content
A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ID-Header
Read
device
0 0 0 0 0 0 FAM_1 FAM_0 NR_PI_5 NR_PI_4 NR_PI_3 NR_PI_2 NR_PI_1 NR_PI_0
Product Code 1
Read
device
0 0 0 0 0 1 PR_ID_7 PR_ID_6 PR_ID_5 PR_ID_4 PR_ID_3 PR_ID_2 PR_ID_1 PR_ID_0
Product Code 2
Read
device
0 0 0 0 1 0 PR_ID_15 PR_ID_14 PR_ID_13 PR_ID_12 PR_ID_11 PR_ID_10 PR_ID_9 PR_ID_8
SPI-Frame-ID
Read
device
0 0 0 0 1 1 BR AR5 AR4 AR3 32 bits 24 bits 16 bits 8 bits
Reserved
Read
device
111111
Reserved, accessing this address is recognized as a failure, the device enters a fail-safe state
(see Table 30: STK_RESET_Q).