Datasheet

Electrical specifications L99H01
16/53 DocID15567 Rev 6
Table 14. Gate drivers for external PowerMOS
Item Symbol Parameter Test condition Min. Typ. Max. Unit
Drivers for external high-side PowerMOS
14.1 I
GHx(on)
Turn on current
(SOURCE stage)
T
j
= 25 °C
(1)
0.3 0.5
(2)
0.8 A
14.2.1
R
GHx
On-resistance of
SINK stage
V
SHx
= 0 V; I
GHx
= 50 mA;
T
j
= 25°C
34 5W
14.2.2
V
SHx
= 0 V; I
GHx
= 50 mA;
T
j
= 125°C
4.5 5.3 7 W
14.3 V
GHxH
Gate on voltage Outputs floating V
SHx
+8V V
SHx
+10V V
SHx
+12V V
14.4 R
GSHx
Passive Gate
clamp resistance
11 13 15 kΩ
Drivers for external low-side PowerMOS
14.5 I
GLx(on)
Turn on current
(SOURCE stage)
T
j
= 25°C
(1)
0.3 0.5
(2)
0.8 A
14.6.1
R
GLx
On-resistance of
SINK stage
V
SLx
= 0 V; I
GHx
= 50 mA;
T
j
= 25°C
34 5W
14.6.2
V
SLx
= 0 V; I
GHx
= 50 mA;
T
j
= 125°C
4.5 5.3 7 W
14.7 V
GLxH
Gate on voltage V
SLx
+8V V
SLx
+10V V
SLx
+ 12 V V
14.8 R
GSLx
Passive gate
clamp resistance
11 13 15 kΩ
Timing of the drivers
14.9 t
GHxHL
Propagation delay
time high to low
V
VS
= 13.5 V; V
SHx
= 0;
R
G
=30 Ω; C
G
=4.7nF
0.8 1.4 1.9 µs
14.10 t
GLxHL
Propagation delay
time low to high
V
VS
= 13.5 V; V
SLx
= 0;
R
G
=30 Ω,; C
G
=4.7nF
0.6 1.2 1.8 µs
14.11 t
GHxr2
Rise time
V
VS
= 13.5 V; V
SHx
= 0;
R
G
=0 Ω; C
G
=4.7nF
45 170 ns
14.12 t
GHxf2
Fall time
V
VS
= 13.5 V; V
SHx
= 0;
R
G
=0 Ω; C
G
=4.7nF
60 210 ns
14.13 t
GLxr2
Rise time
V
VS
= 13.5 V; V
SLx
= 0;
R
G
=0 Ω; C
G
=4.7nF
45 170 ns
14.14 t
GLxf2
Fall time
V
VS
= 13.5 V; V
SLx
= 0;
R
G
=0 Ω; C
G
=4.7nF
60 210 ns
1. Indirect measurement, parameter measured dynamically using 100 nF load capacitor and evaluating the slew rate.
2. Average value.