Datasheet

L9942 Appendix
Doc ID 11778 Rev 7 37/40
Figure 17. Reference generation for PWM control (decay)
Register 0
UP/Down
STEP
Count by
1,2,4,8
A0A1A2A3
MUX
A0A1A2
0 0 0
01 23 01 23 01 23
Current-Profile Table
stored in register2, ...6
A3=0
Adr
A[3..0]
Phase A
Profile 8
Address Calculation
11110
Profile 7
Profile 6
Profile 5
Profile 4
Profile 3
01100
Profile 2
00110
Profile 1
00000
Profile 0
5
5
5
5
5
5
5
5
5
A3=1
Adr
neg(A[3..0])
A3=0
Adr neg(A[3..0])
Phase B
A3=1
Adr
A[3..0]
Register 1
9
5
DIR
0
10
PhaseCounter
StepMode
SR0SR1 0 0
Slew Rate
DM2 DM1 DM0
MUX MUX
01111 01100
DAC Phase B
DAC Phase A
Decay Mode
5 bit DAC
Phase A
5 bit DAC
Phase B
000
DAC Scale
DAC
Full Scale
REF
REF
I
MAX
I
LIMIT B
I
LIMIT A
I
DI
HS1 on
HS2 on
HS1 on
LS2on
0
1
23456787654321012345678765432
1
0
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0123456787654321012345678
7
654321
Current Driver A
Current Driver B
STEP Signal
Adress of Current
Profile Entry
Phase A
Phase Counter
Adress of Current
Profile Entry
Phase B
000
95 mA
100mA * 6/31 = 18.4mA
95mA * 30/31 = 91.9mA
200 uA
10110
11010
11101
10001
11111
Auto Decay
Mixed Decay
Slow Decay
Fast and Slow
Decay
A
I
1
1
Counter value changes after an signal at STEP to next one
depending on selected stepping mode described in figure 1.2
(e.g. during micro stepping to value 2) .
Slow
Decay
Fast
Decay
QA1
QA2
+
-
-
+
-
2mA
+
-
2mA
-
+
-
-
+
-
2mA
+
-
2mA
-
B
I
QB1
I
1000
QB1
QB2
+
-
-
+
HSB1
OC
-
2mA
+
-
2mA
-
+
-
-
+
-
2mA
+
-
LIMIT
2mA
LSB2
-
HS Current
Monitoring
(Overcurrent)
LS Current
Monitoring
(Load Control)
HS Current
Monitoring
(Overcurrent)
HS Current
Monitoring
(Overcurrent)
HSA1
OC
HSB1
OC