Datasheet

Appendix L9942
36/40 Doc ID 11778 Rev 7
Figure 16. Reference generation for PWM control (switch on)
Register 0
UP/Down
STEP
Count by
1,2,4,8
A0A1A2A3
MUX
A0A1A2
0 0 0
01 23 01 23 01 23
Current-Profile Table
stored in register2, ...6
A3=0
Adr
A[3..0]
Phase A
Profile 8
Address Calculation
11110
Profile 7
Profile 6
Profile 5
Profile 4
Profile 3
01100
Profile 2
00110
Profile 1
00000
Profile 0
5
5
5
5
5
5
5
5
5
A3=1
Adr
neg(A[3..0])
A3=0
Adr neg(A[3..0])
Phase B
A3=1
Adr
A[3..0]
Register 1
9
5
DIR
0
10
PhaseCounter
StepMode
SR0SR1 0 0
Slew Rate
DM2 DM1 DM0
MUX MUX
01111 01100
DAC Phase B
DAC Phase A
Decay Mode
5 bit DAC
Phase A
5 bit DAC
Phase B
000
DAC Scale
DAC
Full Scale
REF
REF
I
MAX
I
LIMIT B
I
LIMIT A
I
DI
HS1 on
LS2 on
LS1 on
HS2on
0
1
23456787654321012345678765432
1
0
1
2345678910111213141516171819202122232425262728293031
0123456787654321012345678
7
654321
Current Driver A
Current Driver B
STEP Signal
Adress of Current
Profile Entry
Phase A
Phase Counter
Adress of Current
Profile Entry
Phase B
000
95 mA
100mA * 6/31 = 18.4mA
100mA * 30/31 = 91.9mA
200 uA
10110
11010
11101
10001
11111
A
I
QA1LIM
I
1000
1
1
Counter value changes after an signal at STEP to next one
depending on selected stepping mode described in figure 3
(e.g. during micro stepping to value 2) .
PWM Control With HS Current Monitoring
Overcurrent Detection At LS Switch
QA1
QA2
+
-
-
+
HSA1
LIMIT
-
2mA
+
-
2mA
-
+
-
-
+
LSA2
-
2mA
+
-
2mA
OC
-
B
I
QA2LIM
I
1000
QB1
QB2
+
-
-
+
LSB1
-
2mA
+
-
2mA
OC
-
+
-
-
+
HSB2
LIMIT
-
2mA
+
-
2mA
-
HS Current
Monitoring
(Load control)
LS Current
Monitoring
(Overcurrentl)
HS Current
Monitoring
(Load control)
LS Current
Monitoring
(Overcurrent)