Datasheet

Logic with SPI - electrical characteristics L9942
30/40 Doc ID 11778 Rev 7
6.6 STEP timing
Figure 10. Transfer timing diagram
Figure 11. Input timing
Table 26. STEP timing
Symbol Parameter Test condition Min. Typ. Max. Unit
t
STEPmin
(1)
STEP low or high time - 2 - - µs
1. Parameter guaranteed by design.
A2 A1
time
time
time
time
time
CSN high to low: DO enabled
actual data
DI: data will be accepted on the rising edge of CLK signal
new data
CSN
CLK
DI
DO
Control and Status Register
DO: data will change on the falling edge of CLK signal
status information
fault bit
CSN low to high: actual data is
transfered to registers
old data
123 456 789101101213141510
actual data
A1 A0 D12D11 D10 D9
D8
D7 D6 D5 D4A2 D3 D2 D1 D0
D0
D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
t
CSN_HI,min
fault bit
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
Val id
Val id
CSN
CLK
DI
t
set CSN
t
CLKH
t
set CLK
t
CL KL
t
hold DI
t
set DI
t
CLK