Datasheet

Logic with SPI - electrical characteristics L9942
28/40 Doc ID 11778 Rev 7
6 Logic with SPI - electrical characteristics
VS = 7 to 20 V, VCC = 3.0 to 5.3 V, EN=VCC, T
j
= -40 to 150 °C, I
REF
= -200 A, unless
otherwise specified. The voltages are referred to GND and currents are assumed positive,
when the current flows into the pin.
6.1 Inputs: CSN, CLK, STEP, EN and DI
6.2 DI timing
Table 21. Inputs: CSN, CLK, STEP, EN and DI
Symbol Parameter Test condition Min. Typ. Max. Unit
V
in L
input low level - 0.3*VCC 0.4*VCC - V
V
in H
input high level - - 0.6*VCC 0.7*VCC V
V
in Hyst
input hysteresis - - 0.1*VCC - V
I
CSN in
pull up current at input CSN V
CSN
= VCC -1.5 V, -50 -25 -10 µA
I
CLK in
pull down current at input CLK V
CLK
= 1.5 V 10 25 50 µA
I
DI in
pull down current at input DI V
DI
= 1.5 V 10 25 50 µA
I
STEP in
pull down current at input STEP V
STEP
= 1.5 V 10 25 50 µA
R
EN in
resistance at input EN to GND V
EN in
= VCC 110 510 k
C
in
(1)
input capacitance at input CSN,
CLK, DI and PWM
0 V < VCC < 5.3 V - 10 15 pF
1. Parameter guaranteed by design.
Table 22. DI timing (see Figure 11 and Figure 13)
(1)
Symbol Parameter Test condition Min. Typ. Max. Unit
t
CLK
Clock period VCC = 5 V 250 - - ns
t
CLKH
Clock high time VCC = 5 V 100 - - ns
t
CLKL
Clock low time VCC = 5 V 100 - - ns
t
set CSN
CSN set up time, CSN low before
rising edge of CLK
VCC = 5 V 100 - - ns
t
set CLK
CLK set up time, CLK high before
rising edge of CSN
VCC = 5 V 100 - - ns
t
set DI
DI set up time VCC = 5 V 50 - - ns
t
hold DI
DI hold time VCC = 5 V 50 - - ns
t
r in
Rise time of input signal DI, CLK,
CSN
VCC = 5 V - - 25 ns
t
f in
Fall time of input signal DI, CLK,
CSN
VCC = 5 V - - 25 ns
1. DI timing parameters tested in production by a passed/failed test:
T
j
=-40°C/+25°C: SPI communication @5MHz; T
j
=+125°C: SPI communication @4.25MHz