Datasheet

SPI - control and status registers L9942
26/40 Doc ID 11778 Rev 7
5.6 Register 6
The meaning of the different bits is as follows:
5.7 Register 7
The meaning of the different bits is as follows:
Table 19. Register 6
CLR
ST
(PWM)
Filter Freq. ST
REF
ERR
Open load Current profile 8
Bit 12 11 10 9 8 7 6 5 4 3 2 1 0
Access r w r w r w r w r r r r r w r w r w r w r w
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Name CLR6 SST FT
PWM
Freq.
ST
RREF
Error
Phase
B
Phase
A
I4 I3 I2 I1 I0
I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed See also parameter Ta bl e 12
Phase B Phase A These bits indicate open load at bridges
RREF Error This bit indicates if reference current is OK (150 µA <I
REF
< 250 µA), then is RERR=0.
ST This bit indicates stall detection.
PWM Freq. This bit sets frequency of PWM cycle. FRE=1 frequency 20 kHz, FRE=0 frequency 30 kHz
FT This bit sets filter time in glitch filter. FT=0 T
F
=1.5 µs, FT=1 T
F
= 2.5 µs
SST This bit specifies output PWM to reflect same logical level like bit ST.
CLR6 This bit resets all read only bits to 0 in register 6.
Table 20. Register 7
CLR Temperature VS monitor Overcurrent
Bit 12 11 10 9 8 7 6 5 4 3 2 1 0
Access r w r r r r r r r r r r r r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Name CLR7 TSD TW OV(W) UV HSB2 HSB1 LSB2 LSB1 HSA2 HSA1 LSA2 LSA1
bit7 ... bit0 These bits indicate overcurrent in each low side or highside power transistor.
1 overcurrent failure I > 2 A
OV(W) UV These bits indicates failure at VS (See also parameter Ta bl e 9 )
01 Voltage at pin VS is too low.
10 Voltage at pin VS is too high.
TSD TW These bits indicates temperature failure (See also parameter Ta bl e 7)
01 Only for information set at temperature warning threshold.
10 In case of thermal shutdown all bridges are switched off. It has to reset by bit CLR7.
CLR7 This bit resets all bits to 0 in register 7.