Datasheet

L9942 SPI - control and status registers

Doc ID 11778 Rev 7 25/40

5.4 Register 3

The meaning of the different bits is as follows:

5.5 Register 4 and 5

The meaning of the different bits is as follows:

Table 17. Register 3

Bit

Current profile 3 PWM counter PWM Current profile 2

12 11 10 9 8 7 6 5 4 3 2 1 0

Access r w r w r w r w r w r w r w r w r w r w r w r w r w

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

Name I4 I3 I2 I1 I0 D1 D0 NPW M I4 I3 I2 I1 I0

I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed. See also parameter Tabl e 12

D1 D0

These bits are for threshold value in counter of active time during

signal PWM.

NPWM

This bit switches internal PWM signal of bridge A to pin PWM if it

is set to 0, otherwise pin is in high resistance status.

Table 18. Register 4 and 5

Bit

Current profile 5 (7) PWM counter Current profile 4 (6)

121110987 6 54321 0

Access r w r w r w r w r w r w r w r w r w r w r w r w r w

Reset000000 0 00000 0

Name I4 I3 I2 I1 I0 D4(7) D3(6) D2(5) I4 I3 I2 I1 I0

I4 I3 I2 I1 I0

These bits are loaded needed. in register1 DAC Phase A

or B if needed.