Datasheet

SPI - control and status registers L9942
24/40 Doc ID 11778 Rev 7
5.2 Register 1
The meaning of the different bits is as follows:
5.3 Register 2
The meaning of the different bits is as follows:
:
Table 15. Register 1
Bit
DAC scale DAC phase B DAC phase A
12 11 10 9 8 7 6 5 4 3 2 1 0
Access r w r w r w r r r r r r r r r r
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Name DC2 DC1 DC0 BI4 BI3 BI2 BI1 BI0 AI4 AI3 AI2 AI1 AI0
AI4 AI3 AI2 AI1 AI0
These bits control DAC of
bridge A.
Value depends on address and the value of corresponding
current profile.
BI4 BI3 BI2 BI1 BI0
These bits control DAC of
bridge B.
DC2 DC1 DC0
These bits set full scale range
of limit, e.g. 000 for 100 mA or
111 for e.g. 1500 mA
See also parameter Ta bl e 12.
Table 16. Register 2
Bit
Current profile 1 OV Test only Current profile 0
12 11 10 9 8 7 6 5 4 3 2 1 0
Access r w r w r w r w r w r w r w r w r w r w r w r w r w
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0
Name I4 I3 I2 I1 I0 OVW T1 T0 I4 I3 I2 I1 I0
I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed. See also parameter Ta bl e 12
T1 T0 Should be programmed to 0. -
OVW = 0
In case of an overvoltage event (V-SOV OFF) the outputs are
switched to high impedance state and the Vs Monitor bit OV is
set.
-
OVW = 1
In case of an overvoltage event (V-SOV OFF) the Vs Monitor bit
OV is set. The status of the outputs are unchanged.
-