Datasheet

L9942 Electrical specifications
Doc ID 11778 Rev 7 19/40
Note: Current profile has to pre set with I4 I3 I2 I1 I0 = 11111 and load to register 1.
Output current limit I
QxnLIM
is product of full scale current |I
QxnFS_ |
(bits DC2 DC1 DC0) and
value of DAC Phase A/B (bits I4 I3 I2 I1 I0) in register1.
Values of DAC Phase A and B can read out and depends on set up done before:
1. direction DIR, stepping mode ST1 ST0 and phase counter P4 P3 P2 P1 P0 in register 0 and
2. value of corresponding current profile (for address of current profile entry see also
Figure 3).
Figure 7. Logic to set load current limit
Register 0
UP/Down
STEP
I4 I3 I2 I1 I0
Count by
1,2,4,8
A0A1A2A3
MUX
A0A1A2
0 0 0
012301230123
Current-Profile Table
stored in register2, ...6
A3=0
Adr
A[3..0]
Phase A
Profile 8
Address Calculation
I4 I3 I2 I1 I0
Profile 7
I4 I3 I2 I1 I0
Profile 6
I4 I3
I2 I1 I0
Profile 5
I4 I3 I2 I1 I0
Profile 4
I4 I3 I2 I1 I0
Profile 3
I4 I3 I2 I1 I0
Profile 2
I4 I3 I2
I1 I0
Profile 1
I4 I3 I2 I1 I0
Profile 0
5
5
5
5
5
5
5
5
5
A3=1
Adr
neg(A[3..0])
A3=0
Adr neg(A[3..0])
Phase B
A3=1
Adr
A[3..0]
Register 1
9
5
DIR
P0P1P2P3P4
PhaseCounter
StepMode
SR0SR1 ST1 ST0
Slew Rate
DM2 DM1 DM0
MUX MUX
I0I1I2I3I4I0I1I2I3I4
DAC Phase B
DAC Phase A
Decay Mode
5 bit DA C
Phase A
5 bit DAC
Phase B
DC0DC1DC2
DAC Scale
DAC
Full Scale
REF
REF
I
MAX
I
LIMIT B
LIMIT A
I
DI
QB1
QB2
QA1
QA2
Qx1LIM
I
Qx2LIM
I
QA1LIM
I
1000
QB2LIM
I
1000
QB1LIM
I
1000
QA2LIM
I
1000