Datasheet

5/11
L9825
Diagnostics
V
DG
Diagnostic threshold voltage 0.32·V
CC
0.4·V
CC
V
I
OL
Open load detection sink current V
out
= V
DG
20 100 µA
t
df
Diagnostic detection filter time for
output 1 & 2 on each diagnostic
condition
15 50 µs
Outputs timing
t
don1
Turn ON delay of OUT 1 and 2 NON
1, 2
= 50% to V
OUT
= 0.9·V
bat
NCS = 50% to V
OUT
= 0.9·V
bat
5µs
t
don2
Turn ON delay of OUT 3 to 8 NCS = 50% to V
OUT
= 0.9·V
bat
10 µs
t
doff
Turn OFF delay of OUT 1 to 8 NCS = 50% to V
OUT
= 0.1·V
bat
NON
1, 2
= 50% to V
OUT
= 0.1·V
bat
10 µs
dUon1/dt Turn ON voltage slew-rate For output 3 to 8; 90% to 30% of
V
bat
; R
L
= 500Ω; V
bat
= 16V
0.7 3.5 V/µs
dUon2/dt Turn ON voltage slew-rate For output 1 and 2; 90% to 30%
of V
bat
; R
L
= 500Ω; V
bat
= 16V
210V/µs
dUoff1/dt Turn OFF voltage slew-rate For output 1 to 8; 30% to 90% of
V
bat
; R
L
= 500Ω; V
bat
= 16V
210V/µs
dUoff2/dt Turn OFF voltage slew-rate For output 1 to 8; 30% to 80% of
V
bat
; R
L
= 500Ω; V
bat
= 0.9 · V
clp
215V/µs
Serial diagnostic link (Load capacitor at SDO = 100pF)
f
clk
Clock frequency 50% duty cycle 3 MHz
t
clh
Minimum time CLK = HIGH 160 ns
t
cll
Minimum time CLK = LOW 160 ns
t
pcld
Propagation delay
CLK to data at SDO valid
4.9V ≤ V
CC
≤ 5.1V 100 ns
t
csdv
NCS = LOW to data at SDO
active
100 ns
t
sclch
CLK low before NCS low Setup time CLK to NCS change H/L 100 ns
t
hclcl
CLK change L/H after NCS = low 100 ns
t
scld
SDI input setup time CLK change H/L after SDI data
valid
20 ns
t
hcld
SDI input hold time SDI data hold after CLK change H/L 20 ns
t
sclcl
CLK low before NCS high 150 ns
t
hclch
CLK high after NCS high 150 ns
t
pchdz
NCS L/H to output data float 100 ns
NCS pulse filter time Multiple of 8 CLK cycles
ELECTRICAL CHARACTERISTCS (continued)
(4.5V
≤ V
CC
≤ 5.5V; -40°C ≤ T
J
≤ 150°C; unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit