Datasheet

L9822E Electrical specifications
9/17
V
OREF
Fault refer. voltage
Output progr. OFF
Fault detected if V
O
> V
OREF
1.6 2 V
t
UD
Fault reset delay (after
CE L to H transition)
See Figure 6. 75 250 µs
V
OFF
Output OFF voltage Output pin floating. Output progr. OFF 1V
Input buffer (SI, CE, SCLK and RESET pins)
V
T–
Threshold voltage at
falling edge SCLK only
V
CC
= 5 V ± 10 %
0.2V
CC
0.6
V
V
T+
Threshold voltage at
rising edge SCLK only
V
CC
= 5 V ± 10 %
0.7V
CC
4.15
V
V
H
Hysteresis voltage V
T+
– V
T–
0.85 2.5 V
I
I
Input current V
CC
= 5.50 V, 0 < V
I
< V
CC
– 10 + 10 µA
C
I
Input capacitance 0 < V
I
< V
CC
20 pF
Output buffer (SO pin)
V
SOL
Output low voltage I
O
= 1.6 mA 0.4 V
V
SOH
Output high voltage I
O
= 0.8 mA
V
CC
– 1.3V
V
I
SOtl
Output tristate leakage
current
0 < V
O
< V
CC
, CE pin held high,
V
CC
= 5.25 V
– 20 20 µA
C
SO
Output capacitance 0 < V
O
< V
CC
, CE pin held high 20 pF
I
CC
Quiescent supply current
at V
CC
pin
All outputs progr. ON. I
O
= 0.5 A per
output simultaneously
10 mA
Serial peripheral interface (see Figure 5, timing diagram)
f
op
Operating frequency D.C. 2 MHz
t
lead
Enable lead time 250 ns
t
lag
Enable lag time 250 ns
t
wSCKH
Clock high time 200 ns
t
wSCKL
Clock low time 200 ns
t
su
Data setup time 75 ns
t
H
Data hold time 75 ns
t
EN
Enable time 250 ns
t
DIS
Disable time 250 ns
t
V
Data valid time 100 ns
t
rSO
Rise time (SO output) V
CC
= 20 to 70 % C
L
= 200 pF 50 ns
t
fSO
Fall time (SO output) V
CC
= 70 to 20 % C
L
= 200 pF 50 ns
t
rSI
Rise time SPI inputs
(SCK, SI, CE)
V
CC
= 20 to 70 % C
L
= 200 pF 200 ns
t
fSI
Fall time SPI inputs
(SCLK, SI, CE)
V
CC
= 70 to 20 % C
L
= 200 pF 200 ns
t
ho
Output data hold time 0 µs
Table 5. Electrical characteristics (continued)
(V
CC
= 5 V ± 5 %. T
j
= – 40 to 125 °C ; unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit