Datasheet

Application information L7985
20/43 Doc ID 022446 Rev 3
Equation 21
As seen in Section 5.3, two different kinds of network can compensate the loop. In the
following two paragraphs the guidelines to select the type II and type III compensation
network are illustrated.
6.4.1 Type III compensation network
The methodology to stabilize the loop consists of placing two zeroes to compensate the
effect of the LC double pole, therefore increasing phase margin; then, to place one pole in
the origin to minimize the dc error on regulated output voltage; and finally, to place other
poles far from the zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the type III
compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low
ESR (<1 mΩ), with very high frequency zero, so a type III network is adopted to compensate
the loop.
In Figure 10 the type III compensation network is shown. This network introduces two
zeroes (f
Z1
, f
Z2
) and three poles (f
P0
, f
P1
, f
P2
). They are expressed as:
Equation 22
Equation 23
Q
R
OUT
LC
OUT
R
OUT
ESR+()⋅⋅ ⋅
LC
OUT
R
OUT
ESR⋅⋅+
-------------------------------------------------------------------------------------------------------
R
OUT
V
OUT
I
OUT
--------------- -=,=
f
Z1
1
2π C
3
R
1
R
3
+()⋅⋅
-------------------------------------------------------= f
Z2
1
2π R
4
C
4
⋅⋅
------------------------------------=,
f
P0
0= f
P1
1
2π R
3
C
3
⋅⋅
------------------------------------= f
P2
1
2π R
4
C
4
C
5
⋅
C
4
C
5
+
----------------------
⋅⋅
---------------------------------------------------=,,