Datasheet

L7981 Application informations
Doc ID 15182 Rev 3 25/44
Figure 14. Open loop gain: module bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follow:
1. Choose a value for R
1
, usually between 1kΩ and 5kΩ, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R
4
/R
1
) in order to have the required bandwidth (BW), that means:
Equation 25
Where f
ESR
is the ESR zero:
Equation 26
and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant.
3. Calculate C
4
by placing the zero one decade below the output filter double pole:
Equation 27
4. Then calculate C
3
in order to place the second pole at four times the system bandwidth
(BW):
R
4
f
ESR
f
LC
------------
⎝⎠
⎛⎞
2
BW
f
ESR
----------- -
V
S
V
IN
---------
R
1
⋅⋅⋅=
f
ESR
1
2π ESR C
OUT
⋅⋅
------------------------------------------- -=
C
4
10
2π R
4
f
LC
⋅⋅
-------------------------------=