Datasheet

Application details L6738A
24/32 Doc ID 18134 Rev 2
a) Set the gain R
F
/R
FB
in order to obtain the desired closed loop regulator bandwidth
according to the approximated formula (suggested values for R
FB
are in the range
of some kΩ):
b) Place F
Z1
below F
LC
(typically 0.5*F
LC
):
c) Place F
P1
at F
ESR
:
d) Place F
Z2
at F
LC
and F
P2
at half of the switching frequency:
e) Check that compensation network gain is lower than open loop EA gain before
F
0dB
;
f) Check phase margin obtained (it should be greater than 45°) and repeat if
necessary.
9.2 Layout guidelines
The L6738A provides control functions and high current integrated drivers to implement
high-current step-down DC-DC converters. In this kind of application, a good layout is very
important.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (EMI and losses) power connections (highlighted in
Figure 11) must be a part of a power plane and realized by wide and thick copper traces:
loop must be minimized. The critical components, i.e. the power MOSFETs, must be close
to one another. The use of a multi-layer printed circuit board is recommended.
The input capacitance (C
IN
), or at least a portion of the total capacitance needed, has to be
placed close to the power section in order to eliminate the stray inductance generated by the
copper traces. Low ESR and ESL capacitors are preferred, MLCCs are recommended to be
connected near the HS drain.
Use a proper number of VIAs when power traces have to move between different planes on
the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing
the same high-current trace on more than one PCB layer reduces the parasitic resistance
associated to that connection.
R
F
R
FB
----------
F
0dB
F
LC
------------
∆V
OSC
V
IN
-------------------
⋅=
C
F
1
π R
F
F
LC
⋅⋅
-----------------------------------=
C
P
C
F
2π R
F
C
F
F
ESR
1–⋅⋅⋅
-------------------------------------------------------------------=
R
S
R
FB
F
SW
2F⋅
LC
-------------------- 1–
------------------------------=
C
S
1
π R
S
F
SW
⋅⋅
-------------------------------------=