Datasheet

Application details L6738A
22/32 Doc ID 18134 Rev 2
9 Application details
9.1 Compensation network
The control loop shown in Figure 9 is a voltage mode control loop. The output voltage is
regulated to the internal reference (when present, an offset resistor between FB node and
GND can be neglected in control loop calculation).
Error amplifier output is compared to the oscillator sawtooth waveform to provide a PWM
signal to the driver section. The PWM signal is then transferred to the switching node with
V
IN
amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and V
OUT
. This function has a double pole at frequency F
LC
depending on the L-C
OUT
resonance and a zero at F
ESR
depending on the output capacitor ESR. The DC gain of the
modulator is simply the input voltage V
IN
divided by the peak-to-peak oscillator voltage
∆V
OSC
.
Figure 9. PWM control loop
The compensation network closes the loop joining V
OUT
and EA output with transfer
function ideally equal to -Z
F
/Z
FB
.
Compensation goal is to close to the control loop assuring high DC regulation accuracy,
good dynamic performance and stability. To achieve this, the overall loop needs high DC
gain, high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F
0dB
) can be fixed choosing the right R
F
/R
FB
ratio, however, for
stability, it should not exceed F
SW
/2π. To achieve a good phase margin, the control loop gain
has to cross the 0dB axis with -20dB/decade slope.
For example, Figure 10 shows an asymptotic bode plot of a type III compensation.
L R
C
OUT
ESR
R
F
C
F
C
P
R
FB
C
S
OSC
V
IN
∆V
OSC
+
+
_
_
V
OUT
V
REF
Z
F
Z
FB
PWM
COMPARATOR
ERROR
AMPLIFIER
R
S