Datasheet
Pin connections and functions L6730 - L6730B
8/52 Doc ID 11938 Rev 3
3 Pin connections and functions
Figure 3. Pins connection (top view)
Note: In the L6730B the multifunction pin is: CC/OVP/UVLO.
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
HTSSOP20
10
17
18
19
20
OSC
SS/INH
COMP
FB
GND
SYNCH
PGOOD DELAY
TMASK
EAREF
PGOOD
PHASE
HGATE
BOOT
VCC
VCCDR
LGATE
OCL
OCH
PGND
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
HTSSOP20
10
17
18
19
20
OSC
SS/INH
COMP
FB
GND
SYNCH
PGOOD DELAY
TMASK
EAREF
PGOOD
PHASE
HGATE
BOOT
VCC
VCCDR
LGATE
OCL
OCH
PGND
SINK/OVP/UVLO
Table 4. Pin connection
Pin n. Name Description
1 PGOOD DELAY
A capacitor connected between this pin and GND introduces a delay
between the internal PGOOD comparator trigger and the external signal
rising edge. No delay can be introduced on the falling edge of the
PGOOD signal. The delay can be calculated with the following formula:
2 SYNCH
Two or more devices can be synchronized by connecting the SYNCH pins
together. The device operating with the highest F
SW will be the Master
device. The Slave devices will operate at 180° phase shift from the
Master. The best way to synchronize devices is to set their FSW at the
same value. If it is not used, the SYNCH pin can be left floating.
3
SINK/OVP/UVLO
L6730
CC/OVP/UVLO
L6730B
With this pin it is possible:
To enable-disable the sink mode current capability after SS (L6730);
To enable-disable the constant current OCP after SS (L6730B);
To enable-disable the latch mode for the OVP;
To set the UVLO threshold for the 5 V BUS and 12 V BUS.
The device captures the analog value present at this pin at the start-up
when V
CC
meets the UVLO threshold.
(
)
pFCPGDelay
⋅
=
5.0
[μ
s]