Datasheet

I/O Description L6730 - L6730B
44/52 Doc ID 11938 Rev 3
TP2 This test point is connected to the Tmask pin (see Table 4: Pin connection).
TP3 This test point is connected to the S/O/U pin (see Chapter 5.10 on page 27).
SYNCH
This pin is connected to the synch pin of the controller (see Chapter 5.11 on
page 28).
PWRGD This pin is connected to the PGOOD pin of the controller.
DIP SWITCH
Different positions of the dip switch correspond to different settings of the
multifunction pin (S/O/U) (CC/O/U).
Table 12. Dip switch
UVLO OVP SINK CC
Vsou/V
CCDR
DIP switch State
5V Not latched Not 0 S7 A
5V Not latched Yes 0.2 S1-S7 B
5V Latched Not 0.3 S2-S7 C
5V Latched Yes 0.4 S3-S7 D
12V Not latched Not 0.5 S4-S7 E
12V Not latched Yes 0.6 S5-S7 F
12V Latched Not 0.7 S6-S7 G
12V Latched Yes 1 S1 H
Table 11. I/O functions (continued)
Symbol Function