Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers HTSSOP 20

December 2009 Doc ID 11938 Rev 3 1/52

L6730

L6730B

Adjustable step-down controller with synchronous rectification

Features

■ Input voltage range from 1.8 V to 14 V

■ Supply voltage range from 4.5 V to 14 V

■ Adjustable output voltage down to 0.6 V with

±0.8% accuracy over line voltage and

temperature (0°C~125°C)

■ Fixed frequency voltage mode control

■ t

lower than 100 ns

■ 0% to 100% duty cycle

■ Selectable 0.6 V or 1.2 V internal voltage

reference

■ External input voltage reference

■ Soft-start and inhibit

■ High current embedded drivers

■ Predictive anti-cross conduction control

■ Selectable uvlo threshold (5 V or 12 V BUS)

■ Programmable high-side and low-side R

DS(on)

sense overcurrent protection

■ Switching frequency programmable

from 100 kHz to 1 MHz

■ Master/slave synchronization with 180° phase

shift

■ Pre-bias start up capability (L6730)

■ Selectable source/sink or source only

capability after soft-start (L6730)

■ Selectable constant current or hiccup mode

overcurrent protection after soft-start (L6730B)

■ Power Good output with programmable delay

■ Overvoltage protection with selectable

latched/not-latched mode

■ Thermal shut-down

■ Package: HTSSOP20

Applications

■ High performance / high density DC-DC

modules

■ Low voltage distributed DC-DC

■ niPOL converters

■ DDR memory supply

■ DDR memory bus termination supply

Table 1. Device summary

Order codes Package Packing

L6730 HTSSOP20 Tube

L6730TR HTSSOP20 Tape and reel

L6730B HTSSOP20 Tube

L6730BTR HTSSOP20 Tape and reel

HTSSOP20

www.st.com

Summary of content (52 pages)

PAGE 1
L6730 L6730B Adjustable step-down controller with synchronous rectification Features ■ Input voltage range from 1.8 V to 14 V ■ Supply voltage range from 4.5 V to 14 V ■ Adjustable output voltage down to 0.6 V with ±0.8% accuracy over line voltage and temperature (0°C~125°C) ■ Fixed frequency voltage mode control ■ tON lower than 100 ns ■ 0% to 100% duty cycle ■ Selectable 0.6 V or 1.
PAGE 2
Contents L6730 - L6730B Contents 1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Maximum rating . . . . . .
PAGE 3
L6730 - L6730B Contents 6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.5 Two quadrant or one quadrant operation mode (L6730) . . . . . . . . . . . . . 37 7 L6730 demonstration board . . . . . . . . . . . . . . . . . . .
PAGE 4
Summary description 1 L6730 - L6730B Summary description The controller is an integrated circuit designed using BiCMOS-DMOS, v5 (BCD5) technology that provides complete control logic and protection for high performance, stepdown DC/DC and niPOL converters. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck converter topology. The output voltage of the converter can be precisely regulated down to 600 mV, with a maximum tolerance of ±0.8%, or to 1.
PAGE 5
L6730 - L6730B Summary description 1.1 Functional description Figure 1. Block diagram VCC=4.5V to14V Vin=1.8V to14V OCL PGOOD OCH VCCDR BOOT LDO SS/INH SYNCH Monitor Protection and Ref OSC HGATE Vo OSC PHASE EAREF L6730/B LGATE PGOOD SINK/OVP/UVLO* + 0.6V - 1.2V + PWM PGND E/A TMASK MASKING TIME ADJUSTMENT + FB Note: - GND COMP In the L6730B the multifunction pin is: CC/OVP/UVLO.
PAGE 6
Summary description 1.2 L6730 - L6730B Application circuit Figure 2. Application circuit VCC = 4.5V to 14V RFILT GND VCC CDEC VIN = 1.
PAGE 7
L6730 - L6730B Electrical data 2 Electrical data 2.1 Maximum rating Table 2. Absolute maximum ratings Symbol Parameter VCC Value Unit -0.3 to 18 V 0 to 6 V 0 to VBOOT - VPHASE V BOOT -0.3 to 24 V PHASE -1 to 18 VCC to GND and PGND, OCH, PGOOD VBOOT - VPHASE Boot voltage VHGATE - VPHASE VBOOT VPHASE PHASE spike, transient < 50ns (FSW = 500kHz) SS, FB, EAREF, SYNC, OSC, OCL, LGATE, COMP, S/O/U, TMASK, PGOODELAY, VCCDR OCH Pin PGOOD Pin OTHER PINS 2.
PAGE 8
Pin connections and functions 3 L6730 - L6730B Pin connections and functions Figure 3. Pins connection (top view) PGOOD DELAY 1 20 PGOOD SYNCH 2 19 VCC 3 18 VCCDR 4 17 LGATE 5 16 PGND 6 15 BOOT 7 14 HGATE SS/INH 8 13 PHASE EAREF 9 12 OCH OSC 10 11 OCL SINK/OVP/UVLO TMASK GND FB COMP HTSSOP20 Note: In the L6730B the multifunction pin is: CC/OVP/UVLO. Table 4. Pin n.
PAGE 9
L6730 - L6730B Table 4. Pin n. Pin connections and functions Pin connection (continued) Name Description 4 TMASK The user can select two different values for the leading edge blanking time on the peak overcurrent protection by connecting this pin to VCCDR or GND. The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold. 5 GND All the internal references are referenced to this pin. Connect to the PCB signal ground.
PAGE 10
Pin connections and functions Table 4. Pin n. L6730 - L6730B Pin connection (continued) Name Description A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current generator sources a current of 100μA (IOCL) from this pin to ground through the external resistor (ROCL).
PAGE 11
L6730 - L6730B 4 Electrical characteristics Electrical characteristics VCC = 12 V, TA = 25°C unless otherwise specified Table 5. Electrical characteristics Symbol Parameter Test condition VCC stand by current OSC = open; SS to GND VCC quiescent current OSC= open; HG = open, LG = open, PH=open Turn-ON VCC threshold VOCH = 1.7V Turn-OFF VCC threshold Min. Typ. Max. Unit 7 9 8.5 10 4.0 4.2 4.4 VOCH = 1.7V 3.6 3.8 4.0 Turn-ON VCC threshold VOCH = 1.7V 8.3 8.6 8.
PAGE 12
Electrical characteristics Table 5. L6730 - L6730B Electrical characteristics (continued) Symbol IFB Parameter I.I. bias current Test condition VFB = 0V Ext Ref Clamp VOFFSET Min. Typ. Max. Unit 0.290 0.5 μA 2.3 V Error amplifier offset Vref = 0.6V GV Open loop voltage gain Guaranteed by design 100 dB GBWP Gain-bandwidth product Guaranteed by design 10 MHz Slew-rate COMP = 10pF Guaranteed by design 5 V/μs RHGATE_ON High side source resistance VBOOT - VPHASE = 5V 1.
PAGE 13
L6730 - L6730B Electrical characteristics Table 6. Symbol Thermal characterizations (VCC = 12 V) Parameter Test condition Min Typ Max Unit OSC = OPEN; TJ = 0°C~ 125°C 376 400 424 kHz TJ = 0°C~ 125°C 1.188 1.2 1.212 V TJ = -40°C~ 125°C 1.185 1.2 1.212 V TJ = 0°C~ 125°C 0.596 0.6 0.605 V TJ = -40°C~ 125°C 0.593 0.6 0.605 V Oscillator fOSC Initial accuracy Output voltage (1.2V MODE) VFB Output voltage Output voltage (0.
PAGE 14
Device description L6730 - L6730B 5 Device description 5.1 Oscillator The switching frequency is internally fixed to 400 kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging an internal capacitor (FSW = 400 kHz). This current can be varied using an external resistor (RT) connected between OSC pin and GND or VCCDR in order to change the switching frequency. Since the OSC pin is maintained at fixed voltage (typ. 1.
PAGE 15
L6730 - L6730B 5.2 Device description Internal LDO An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC pin and the output (5 V) is the VCCDR pin (see Figure 5). Figure 5. 4.5V÷14V 5.3 LDO block diagram LDO Bypassing the LDO to avoid the voltage drop with low Vcc The LDO can be by passed by providing 5 V voltage directly to VCCDR. In this case Vcc and VCCDR pins must be shorted together as shown in Figure 6.
PAGE 16
Device description Figure 6. 5.4 L6730 - L6730B Bypassing the LDO Internal and external references It is possible to set two internal references, 0.6 V and 1.2 V, or provide an external reference from 0 V to 2.5 V. The maximum value of the external reference depends on the VCC: with VCC = 4 V the clamp operates at about 2 V (typ.), while with VCC greater than 5 V the maximum external reference is 2.5 V (typ).
PAGE 17
L6730 - L6730B 5.5 Device description Error amplifier Figure 7. Error amplifier reference VCCDR 0.6V EAREF 1.2V EXT 100K Error Amplifier Ref. 2.5V 5.6 Soft-start When both VCC and VIN are above their turn-on thresholds (VIN is monitored by the OCH pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a ramp is generated charging the external capacitor CSS with an internal current generator.
PAGE 18
Device description L6730 - L6730B The output of the error amplifier is clamped with this voltage (Vss) until it reaches the programmed value. No switching activity is observable if VSS is lower than 0.5 V and both MOSFETs are off. When Vss is between 0.5 V and 1.1 V the low-side MOSFET is turned on because the output of the error amplifier is lower than the valley of the triangular wave and so the duty-cycle is 0%. As VSS reaches 1.1 V (i.e.
PAGE 19
L6730 - L6730B Device description protection on page 21) but not enter into HICCUP mode. The soft-start phase ends when VSS reaches 3.5 V. After that the over current-protection triggers the HICCUP mode (L6730). With the L6730B there is the possibility to set the HICCUP mode or the constant current mode after the soft-start acting on the multifunction pin CC/O/U. With the L6730 the low-side MOSFET(s) management after soft-start phase depends on the S/O/U pin state (see related section).
PAGE 20
Device description L6730 - L6730B Figure 12. Sink mode disabled: Inductor current during and after soft-start (L6730) Vout Vss Vcc IL 5.7 Driver section The high-side and low-side drivers allow for the use of different types of power MOSFETs (also multiple MOSFETs to reduce the RDSON), maintaining fast switching transitions. The low-side driver is supplied by VCCDR while the high-side driver is supplied by the BOOT pin.
PAGE 21
L6730 - L6730B Device description negative. This situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates. Figure 13. Dead times 5.8 Monitoring and protection The output voltage is monitored by the FB pin. If it is not within ±10% (typ.) of the programmed value, the Power-Good (PGOOD) output is forced low. The PGOOD signal can be delayed by adding an external capacitor on PGDelay pin (see Table 4: Pin connection and Figure 14.
PAGE 22
Device description L6730 - L6730B turned on until VCC is toggled (see Figure 16). In case of latched-mode OVP the OSC pin is forced high (4.5 V typ) if an over voltage is detected. Figure 14. PGOOD signal FB PGOOD 2ms/Div. Figure 15.
PAGE 23
L6730 - L6730B Device description Figure 16. OVP latched LGate OSC FB There is an electrical network between the output terminal and the FB pin and therefore the voltage at this pin is not a perfect replica of the output voltage. If the converter can sink current, in the most of cases the low-side will be turned on before the output voltage exceeds the over-voltage threshold because the error amplifier will throw off balance in advance.
PAGE 24
Device description L6730 - L6730B Figure 17. OVP with sink enabled: the low-side MOSFET is turned-on in advance VOUT 109% VFB LGate Figure 18. OVP with sink disabled: delay on the OVP operation 126% VOUT VFB LGate The L6730B can always sink current and so the OVP will operate always in advance.
PAGE 25
L6730 - L6730B Device description enters in HICCUP mode (L6730): the high-side and low-side MOSFET(s) are turned off, the soft-start capacitor is discharged with a constant current of 10 µA and when the voltage at the SS pin reaches 0.5 V the soft-start phase restarts. During the soft-start phase the OCP provides a constant-current-protection.
PAGE 26
Device description L6730 - L6730B Figure 20. Peak overcurrent-protection in constant-current-protection (L6730B) VOUT Peak th IL IOUT TON Figure 21. Peak OCP in case of heavy overcurrent (L6730B) VOUT IL IOUT If the current is higher than the valley OCP threshold during the off-time, the high-side MOSFET(s) will not be turned ON. In this way the maximum current can be limited (Figure 22).
PAGE 27
L6730 - L6730B Device description Working with a 12 V BUS, setting the UVLO at 8.6 V can be very helpful to limit the input current in case of BUS fall. Figure 22. Valley OCP (L6730B) VOUT Valley th IL TOFF 5.9 TOFF Adjustable masking time By connecting the masking time pin to VCCDR or GND it is possible to select two different values for the peak current protection leading edge blanking time.
PAGE 28
Device description L6730 - L6730B Table 7 shows how to set the different options through an external resistor divider: Figure 23. External resistor VCCDR R1 L6730/B S/O/U CC/O/U R2 Table 7. 5.11 S/O/U and CC/O/U pin R1 R2 VSOU/VCCDR UVLO OVP SINK CC N.C 0Ω 0 5V BUS Not latched Not 11KΩ 2.7KΩ 0.2 5V BUS Not latched Yes 6.2KΩ 2.7KΩ 0.3 5V BUS Latched Not 4.3KΩ 2.7KΩ 0.4 5V BUS Latched Yes 2.7KΩ 2.7KΩ 0.5 12V BUS Not latched Not 1.8KΩ 2.7KΩ 0.
PAGE 29
L6730 - L6730B Device description The phase shift between master and slaves is approximately done 180°. Figure 24. Synchronization PWM SIGNALS 5.12 INDUCTOR CURRENTS Thermal shutdown When the junction temperature reaches 150°C ±10°C, the device enters in thermal shutdown. Both MOSFETs are turned OFF and the soft-start capacitor is rapidly discharged with an internal switch.
PAGE 30
Device description L6730 - L6730B Figure 25. 14 V -> 0.5 V@820 kHz, 5 A 50ns 5.14 Bootstrap anti-discharging system This built-in anti-discharging system keeps the voltage going across the bootstrap capacitor from going below 3.3 V. An internal comparator senses the voltage across the external bootstrap capacitor and helps to keep it charged, eventually turning on the low-side MOSFET for approximately 200 ns.
PAGE 31
L6730 - L6730B 5.14.1 Device description Fan power supply failure In many applications the fan is driven by a DC motor that uses a DC/DC converter. Often only the speed of the motor is controlled by varying the voltage applied to the input terminal and there is no control on the torque because the current is not directly controlled. The current has to be limited in case of overload or short-circuit, but without stopping the motor.
PAGE 32
Device description L6730 - L6730B effectively turned-on and the regulation can be lost. Thanks to the “bootstrap antidischarging system” the bootstrap cap is always kept charged. The following picture shows the behaviour of the device in the following conditions: 12 V -> 3.3 V@0 A. It can be observed that between two pulses trains the low-side is turned-on in order to keep the bootstrap cap charged. Figure 27. 12 V -> 3.
PAGE 33
L6730 - L6730B Application details 6 Application details 6.1 Inductor design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple current (ΔIL) between 20% and 30% of the maximum output current.
PAGE 34
Application details 6.2 L6730 - L6730B Output capacitors The output capacitors are basic components for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During a load transient, the output capacitors supply the current to the load or absorb the current stored into the inductor until the converter reacts.
PAGE 35
L6730 - L6730B 6.4 Application details Compensation network The loop is based on a voltage mode control (Figure 29). The output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide a pulse-width modulated (PWM) with an amplitude of VIN at the PHASE node. This waveform is filtered by the output filter.
PAGE 36
Application details L6730 - L6730B 0 dB axis with -20 dB/decade slope and a phase margin greater than 45°.
PAGE 37
L6730 - L6730B Two quadrant or one quadrant operation mode (L6730) After the soft-start phase the L6730 can work in source only (one quadrant operation mode) or in sink/source (two quadrant operation mode), depending on the setting of the multifunction pin (see Chapter 5.10 on page 27). The choice of one or two quadrant operation mode is related to the application.
PAGE 38
L6730 demonstration board L6730 - L6730B 7 L6730 demonstration board 7.1 Description L6730 demonstration board realizes in a four layer PCB a step-down DC/DC converter and shows the operation of the device in a general purpose application. The input voltage can range from 4.5 V to 14 V and the output voltage is at 3.3 V. The module can deliver an output current in excess of 30 A. The switching frequency is set at 400 kHz (controller freerunning FSW) but it can be increased up to 1 MHz.
PAGE 39
L6730 - L6730B 7.2 L6730 demonstration board PCB layout Figure 33. Top layer Figure 34. Power ground layer Figure 35. Signal ground layer Figure 36.
PAGE 40
L6730 demonstration board L6730 - L6730B Figure 37. Demonstration board schematic Table 8. 40/52 Demonstration board part list Reference Value Manufacturer Package Supplier R1 820Ω Neohm SMD 0603 IFARCAD R2 0Ω Neohm SMD 0603 IFARCAD R3 N.C.
PAGE 41
L6730 - L6730B Table 8. L6730 demonstration board Demonstration board part list (continued) Reference Value Manufacturer Package Supplier R14 1K 1% 100mW Neohm SMD 0603 IFARCAD R15 1K 1% 100mW Neohm SMD 0603 IFARCAD R16 4K7 1% 100mW Neohm SMD 0603 IFARCAD R17 N.C. R18 2.2Ω Neohm SMD 0603 IFARCAD R19 2.2Ω Neohm SMD 0603 IFARCAD R20 10K 1% 100mW Neohm SMD 0603 IFARCAD R21 N.C. R22 N.C.
PAGE 42
L6730 demonstration board Table 9. L6730 - L6730B Other inductor manufacturer Manufacturer Series Inductor value (µH) Saturation current (A) WURTH ELEKTRONIC 744318180 1.8 20 SUMIDA CDEP134-2R7MC-H 2.7 15 EPCOS HPI_13 T640 1.4 22 TDK SPM12550T-1R0M220 1 22 TOKO FDA1254 2.2 14 HCF1305-1R0 1.15 22 HC5-1R0 1.3 27 Series Capacitor value (µF) Rated voltage (V) C4532X5R1E156M 15 25 C3225X5R0J107M 100 6.
PAGE 43
L6730 - L6730B 8 I/O Description I/O Description Figure 38. Demonstration board Table 11. I/O functions Symbol Input (Vin-Gin) Function The input voltage can range from 1.8V to 14V. If the input voltage is between 4.5V and 14V it can supply also the device (through the VCC pin) and in this case the pin 1 and 2 of the jumper G1 must be connected together. The output voltage is fixed at 3.
PAGE 44
I/O Description L6730 - L6730B Table 11. I/O functions (continued) Symbol TP2 This test point is connected to the Tmask pin (see Table 4: Pin connection). TP3 This test point is connected to the S/O/U pin (see Chapter 5.10 on page 27). SYNCH This pin is connected to the synch pin of the controller (see Chapter 5.11 on page 28). PWRGD This pin is connected to the PGOOD pin of the controller. DIP SWITCH Table 12.
PAGE 45
L6730 - L6730B Efficiency The following figures show the demo board efficiency versus load current for different values of input voltage and switching frequency: Figure 39. Demonstration board efficiency 400 kHz Fsw=400KHz VO = 3.3V EFFICIENCY 95.00% 90.00% VIN = 5V 85.00% VIN = 12V 80.00% 75.00% 1 3 5 7 9 11 13 15 Iout (A) Figure 40. Demonstration board efficiency 645 kHz Fsw=645KHz VO = 3.3V 95.00% EFFICIENCY 9 Efficiency 90.00% VIN = 5V 85.00% 80.00% VIN = 12V 75.00% 70.
PAGE 46
Efficiency L6730 - L6730B Figure 41. Demonstration board efficiency 1 MHz Fsw=1MHz VO = 3.3V 95.00% VIN = 5V EFFICIENCY 90.00% 85.00% 80.00% VIN = 12V 75.00% 70.00% 65.00% 60.00% 1 3 5 7 9 11 13 15 Iout (A) Figure 42. Efficiency with 2xSTS12NH3LL+2XSTSJ100NH3LL EFFICIENCY (%) 12V-->3.3V 0.96 0.95 0.94 0.93 0.92 0.91 0.9 0.89 0.88 0.
PAGE 47
L6730 - L6730B POL demonstration board 10 POL demonstration board 10.1 Description A compact demonstration board has been designed to manage currents in the range of 1015 A. Figure 39 shows the schematic and Table 10 the part list. Multi-layer-ceramiccapacitors (MLCCs) have been used on the input and the output in order to reduce the overall size. Figure 43. Pol demonstration board schematic Table 13.
PAGE 48
POL demonstration board Table 13. L6730 - L6730B Pol demonstration board part list (continued) Reference Value Manufacturer Package Supplier R11 15Ω 1% 100mW Neohm SMD 0603 IFARCAD R12 4K7 1% 100mW Neohm SMD 0603 IFARCAD R13 1K 1% 100mW Neohm SMD 0603 IFARCAD R14 2.2Ω Neohm SMD 0603 IFARCAD R15 2.2Ω Neohm SMD 0603 IFARCAD C1-C7 220nF Kemet SMD 0603 IFARCAD C6- C19-C20-C9 100nF Kemet SMD 0603 IFARCAD C2 1nF Kemet SMD 0603 IFARCAD C11 N.C.
PAGE 49
L6730 - L6730B 11 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 14. HTSSOP20 mechanical data mm inch Dim. Min. Typ. Max. Min. Typ. Max. A 1.200 0.047 A1 0.150 0.006 A2 0.800 b 1.050 0.031 0.
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Package mechanical data L6730 - L6730B Figure 45.
PAGE 51
L6730 - L6730B 12 Revision history Revision history Table 15. Document revision history Date Revision Changes 21-Dec-2005 1 Initial release 29-May-2006 2 New template, thermal data updated 07-Dec-2009 3 Updated Table 4 on page 8 and added Section 1.
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L6730 - L6730B Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.