Datasheet
Application information L6699
16/38 Doc ID 022835 Rev 2
Note that the “Driving logic…” block sets a minimum deadtime T
D_MIN
(≈ 230 ns) below
which T
D
cannot go, to prevent simultaneous conduction of the high-side and the low-side
switch, and also a maximum deadtime T
D_MAX
to guarantee proper operation of the half
bridge. T
D_MAX
is internally set at either 700 ns or one fourth of the oscillator cycle,
whichever is shorter.
Figure 9. Detailed view of deadtime during low-to-high transition of half bridge
midpoint
The actual deadtime T
D
that can be observed during operation does not depend only on the
adjustment circuit of
Figure 7
. This fact can be explained with the aid of the oscilloscope
image shown in
Figure 9
.
It illustrates a detailed view of the low-to-high transition of the half bridge midpoint
(waveform labeled HB) along with the high-side gate-drive (HVG), the low-side gate-drive
(LVG) and the oscillator voltage on pin CF (OSC). Obviously, the information that follows
applies to the high-to-low transition as well.
Figure 7. Adaptive deadtime: principle
schematic
Figure 8. Relevant timing diagrams
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