Datasheet

Application information L6591
32/41 Doc ID 14821 Rev 6
Equation 6
which, solved for R
H
and R
L
, yields:
Equation 7
While the line undervoltage is active the startup generator keeps on working but there is no
PWM activity, therefore the Vcc voltage continuously oscillates between the startup and the
UVLO thresholds, as shown in the timing diagram of
Figure 52 .
The LINE pin, while the device is operating, is a high impedance input connected to high
value resistors, it is therefore prone to pick-up noise, which may alter the OFF threshold or
give origin to undesired switch-off of the IC during ESD tests. It is possible to bypass the pin
to ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind.
Tie to Vcc (#9) with a 220 to 330 kΩ resistor if the function is not used.
6.9 Soft-start and delayed latched shutdown upon overcurrent
At device startup, a capacitor (Css) connected between the SS pin (#4) and ground is
charged by an internal current generator, I
SS1
, from zero up to about 2 V, where it is
clamped. During this ramp, the overcurrent setpoint progressively raises from zero the final
value (0.8 V). The time needed for the overcurrent setpoint to reach its steady-state value,
referred to as soft-start time, is approximately:
Equation 8
During the ramp, the MOSFET duty cycle increases progressively, therefore controlling the
startup inrush current. Furthermore, all the functions that monitor the voltage on the COMP
pin are disabled.
The soft-start pin is also invoked whenever the control voltage (COMP) saturates high,
which reveals an open-loop condition for the feedback system. This condition very often
occurs at startup, but may also be caused by either a control loop failure or a converter
overload/short-circuit.
LH
OFF
L
6
H
ON
R
25.1
R
25.1Vin
R
25.1
1015
R
25.1Vin
=
−
+⋅=
−
−
25.1Vin
25.1
RR;
1015
VinVin
R
OFF
HL
6
OFFON
H
−
=
⋅
−
=
−
1SS
SS
SS
I
C
8.0T =