Datasheet

L6591 Application information
Doc ID 14821 Rev 6 29/41
During the negative-going ramp of the sawtooth, a clock pulse is released. A T-flip-flop,
along with a logic circuit, separates the odd and the even clock pulses. The even ones turn
off the low-side MOSFET first and, after a dead time T
d
, turn on the high-side MOSFET.
Normally, the high-side MOSFET is turned off (and the low-side MOSFET turned on after
the deadtime T
d
) in response to the control loop; in the case of overload, it is the overcurrent
comparator to do the job or, in the case of open control loop, the odd clock pulses limit the
maximum ON-time within one oscillator cycle. In this way, the maximum duty cycle is limited
right below 50% and the operating frequency of the converter is half that of the oscillator.
Precisely, with reference to the waveforms in
Figure 50
, where T
sw
= 2/f
osc
, the maximum
achievable duty cycle is:
Equation 4
At startup, the first clock pulse turns on the low-side MOSFET for 10 oscillator cycles to
charge the bootstrap capacitor and then the high-side MOSFET switches on. When the IC
resumes switching during burst mode operation, the first clock pulse turns on the low-side
MOSFET first to charge the bootstrap capacitor, and just after the second clock pulse the
high-side MOSFET switches on. In this way the bootstrap capacitor is always charged and
ready to supply the high-side floating driver. The oscillator waveforms are illustrated in
Figure 50
as well.
The deadtime T
d
equals the duration of the negative-going ramp of the oscillator sawtooth
plus an internal delay of 125 ns; therefore, it depends on the timing capacitor C
T
and the
resistor R
T
and is given by the approximate relationship:
Equation 5
There is an internal 325 ns limit to the minimum T
d
value, to make sure that no hazardous
condition of shoot-through can be generated, however it is recommended not to use
capacitor values lower than 220 pF.
()
oscd
SW
d
SW
d
SW
max
fT15.0
T
T
5.0
T
T
2
T
D ==
=
9
T
3
Td
10125
R
05.3
1054.2
1.2
CT
+
=