Datasheet

Application information L6591
28/41 Doc ID 14821 Rev 6
Figure 47. Operation after latched disable activation: timing diagram
This function is useful to easily implement a latched over temperature protection by biasing
the pin with a divider from VREF, where the upper resistor is an NTC physically located
close to a heating element like the MOSFET, or the secondary diode or the transformer. An
OVP can be implemented as well, e.g. by sensing the output voltage and transferring an
overvoltage condition via an optocoupler.
6.6 Oscillator and deadtime programming
The oscillator is programmed externally by means of a resistor-capacitor network (R
T
, C
T
)
connected from pin OSC (#5) to VREF (#6) and to ground respectively. Once the oscillator
frequency and the deadtime duration is chosen, the values of RT and CT can be calculated
as:
Equation 1
Equation 2
After having selected the commercial values for R
T
and C
T
, the oscillator frequency (f
osc
)
can be verified with good approximation using the following formula:
Equation 3
AM13263v1
Vcc
LVG, HVG
Vin
t
t
t
t
4.5V
DIS
HVgenera to r i s turn ed on
PFC_STOP
Vcc
on
Vc c
off
Vcc
re sta rt
VH
sta rt
Vcc
on
-1
Disable la tc h i s re set h ere
HV gen erator tu rn-on is disabled here
Inpu t sou rce is re moved he re
()
9
dosc
T
10125Tf
1150
50R
−
⋅−
+=
()
50RR
1200R
f
1
39.1C
TT
T
osc
T
−
−
⋅⋅=
))1150R(C(
39.1
f
TT
osc
+
≈