Datasheet

Application information L6591
26/41 Doc ID 14821 Rev 6
Figure 45. How the L6591 can switch off a PFC controller at light load
6.3 PWM control block
The device is specific to secondary feedback. Typically, there is a TL431 at the secondary
side and an optocoupler that transfers output voltage information to the PWM control at the
primary side, crossing the isolation barrier. The PWM control input (pin #7, COMP) is driven
directly by the phototransistor’s collector (the emitter is grounded) to modulate the duty
cycle. It is recommended to place a small filter capacitor between the pin and GND (#11), as
close to the IC as possible to reduce switching noise pick-up, to set a pole in the output-to-
control transfer function.
6.4 PWM comparator, PWM latch and hiccup mode OCP
The PWM comparator senses the voltage across the current sense resistor (Rs) and, by
comparing it with the programming signal derived by the voltage on pin COMP (#7),
determines the exact time when the high-side MOSFET is to be switched off. The PWM
latch avoids spurious switching, which may be caused by the noise generated (“double-
pulse suppression”).
A second comparator senses the voltage on the current sense input and shuts the IC down
if the voltage at the pin exceeds 1.5 V. Such an anomalous condition is typically generated
by either a short-circuit of one of the secondary rectifiers or a shorted secondary winding or
a saturated transformer. This condition is latched as long as the IC is supplied; therefore if
the IC is supplied by an external source, it is necessary to disconnect the source to restart
the IC.
To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the
first time the comparator is tripped the protection circuit enters a “warning state”. If, in the
next switching cycle, the comparator is not tripped, a temporary disturbance is assumed and
the protection logic is reset in its idle state; if the comparator is tripped again a real
malfunction is assumed and the L6591 is stopped.
If the device is self-supplied, no energy is coming from the self-supply circuit, the voltage on
the Vcc capacitor then decays and crosses the UVLO threshold after some time, which
clears the latch. The internal startup generator is still off and the Vcc voltage still needs to
then go below its restart voltage before the Vcc capacitor is charged again and the IC
restarted. Ultimately, either of the above mentioned failures results in a low-frequency
intermittent operation (hiccup mode operation), with very low stress on the power circuit.
The timing diagram of
Figure 46 illustrates this operation.
AM13261v1
L6591
PFC_STOP8
L6562
6
Vref
ZCD
5.6 k
47
k
BC547
BC547
L6591
PFC_STOP8
L6 563
PFC_O
K
(AC_OK)
L6591
PFC_STOP8
L6562
6
Vref
ZCD
5.6 k
47 k
BC547
BC547
L6591
PFC_STOP8
L6 563
PFC_O
K
(AC_OK)