Datasheet

Application information L6591
24/41 Doc ID 14821 Rev 6
Figure 42. Timing diagram showing short-circuit behavior
(SS pin clamped below 5 V)
6.2 Operation at no load or very light load
When the PWM control voltage at the COMP pin falls below a threshold located at 1.75 V,
the IC is disabled with both the high-side and the low-side MOSFET kept in OFF-state, the
oscillator stopped and the quiescent consumption very much reduced to minimize Vcc
capacitor discharge.
The control voltage now increases as a result of the feedback reaction to the energy delivery
stop and, as it exceeds 1.82 V, the IC restarts switching. After a while, the control voltage
goes down again in response to the energy burst and stops the IC. In this way the converter
works in a burst mode fashion with a nearly constant peak current. A further load decrease
then causes a frequency reduction, which can go down even to few hundred hertz, therefore
minimizing all frequency-related losses and making it easier to comply with energy saving
regulations. The timing diagram of
Figure 43 illustrates this kind of operation, showing the
most significant signals.
If it is necessary to decrease the intervention threshold of the burst mode operation, this can
be done by adding a small DC offset on the current sense pin, as shown in
Figure 44.
Note: The offset reduces the available dynamics of the current signal; therefore, the value of the
sense resistor must be determined taking this offset into account.
AM13258v1
Vcc
LV G ,HVG
Vcc_O K