Datasheet

L6591 Application information
Doc ID 14821 Rev 6 23/41
Figure 41. Timing diagram: normal power-up and power-down sequences
At converter power-down the system loses regulation as soon as the input voltage is so low
that either peak current or maximum duty cycle limitation is tripped. Vcc then drops and
stops IC activity as it falls below the UVLO threshold (10.5 V typ.). The Vcc_OK signal is de-
asserted as the Vcc voltage goes below a threshold Vcc
rest
located at about 5 V. The HV
generator can now restart but, if Vin < Vin
start
, as shown in Figure 41 , HV_EN is de-asserted
too and the HV generator is disabled. This prevents converter restart attempts and ensures
monotonic output voltage decay at power-down.
The low restart threshold Vcc
rest
ensures that, during short-circuits, the restart attempts of
the L6591 has a very low repetition rate, as shown in the timing diagram of
Figure 42 , and
that the converter works safely with extremely low power throughput.
The restart threshold of the HV generator is changed when any latched disable function of
the IC is invoked to ensure a real latch-off. For more details see
Section 6.5 .
AM13257v1
Vcc
HVG, LVG
HV_EN
Vcc
on
Vcc
off
Vcc
re start
t
t
t
t
Vi n
VH
start
I
charge
0.75 mA
t
t
Vc c_ OK
ffo-rewoPno-rewoPNormal
operation
regulation is lo sthere
PFC_S TOP