Datasheet
L6566B Application information
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This function is useful to implement a latched overtemperature protection very easily by
biasing the pin with a divider from VREF, where the upper resistor is an NTC physically
located close to a heating element like the MOSFET, or the transformer. The DIS pin is a
high impedance input, thus it is prone to pick up noise, which might give origin to undesired
latch-off of the device. It is possible to bypass the pin to ground with a small film capacitor
(e.g. 1-10 nF) to prevent any malfunctioning of this kind.
Figure 20. Operation after latched disable activation: timing diagram
5.10 Soft-start and delayed latched shutdown upon overcurrent
At device start-up, a capacitor (C
SS
) connected between the SS pin (14) and ground is
charged by an internal current generator, I
SS1
, from zero up to about 2 V where it is
clamped. During this ramp, the overcurrent setpoint progressively rises from zero to the
value imposed by the voltage on the VFF pin (15, see
Section 5.6: PWM comparator, PWM
latch and voltage feedforward blocks on page 27
); MOSFET’s conduction time increases
gradually, hence controlling the start-up inrush current. The time needed for the overcurrent
setpoint to reach its steady state value, referred to as soft-start time, is approximately:
Equation 12
During the ramp (i.e. until V
SS
= 2 V) all the functions that monitor the voltage on pin COMP
are disabled.
Vcc
(pin 5)
GD
(pin 4)
Vin
Vcc
ON
Vcc
ON
-0.5
t
t
t
t
4.5V
Vcc
OFF
DIS
(pin 8)
Vcc
restart
V
HVstart
HV generator is turned on
HV generator turn-on is disabled here
Input source is removed here
t
AC_OK
(pin 16)
Vth
Disable latch is reset here
Restart is quicker
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−==
3
V
1
I
Css
)V(V
I
Css
T
VFF
1SS
VFFcsx
1SS
SS